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ORCIDVishal Sharma 0004
Person information
- affiliation: Indian Institute of Technology Indore, VLSI Circuit and System Design Lab, India
Other persons with the same name
- Vishal Sharma — disambiguation page
- Vishal Sharma 0001
![[0000-0001-7470-6506]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0001-7470-6506")
— Queen's University Belfast, UK (and 3 more) - Vishal Sharma 0002 — Aston University, Aston Institute of Photonic Technology, Birmingham, UK
- Vishal Sharma 0003 — Indian Institute of Technology Jodhpur, Rajasthan, India
- Vishal Sharma 0005 — Utah State University, Plant, Soils and Climate Department, Logan, UT, USA
- Vishal Sharma 0006 — Georgia Institute of Technology, USchool of Interactive Computing, Atlanta, GA, USA
- Vishal Sharma 0007 — Bharati Vidyapeeth's College of Engineering, Department of Computer Science and Engineering, New Delhi, India
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2020 – today
- 2024
[j7]Narendra Singh Dhakad, Eshika Chittora, Gopal Raut, Vishal Sharma, Santosh Kumar Vishvakarma:
In-Memory Computing with 6T SRAM for Multi-operator Logic Design. Circuits Syst. Signal Process. 43(1): 646-660 (2024)- [j6]Junjie Mu, Lu Lu, Ju Eon Kim, Byung-Kwon An, Vishal Sharma, Arya Jagath Lekshmi, Putu Andhita Dananjaya, Weng Hong Lai, Wen Siang Lew, Tony Tae-Hyoung Kim:
A 1-Mb RRAM Macro With 9.8 ns Read Access Time Utilizing Dynamic Reference Voltage for Reliable Sensing Operation. IEEE Trans. Circuits Syst. II Express Briefs 71(5): 2564-2568 (2024) - 2023
- [j5]Gopal Raut, Jogesh Mukala, Vishal Sharma, Santosh Kumar Vishvakarma:
Designing a Performance-Centric MAC Unit with Pipelined Architecture for DNN Accelerators. Circuits Syst. Signal Process. 42(10): 6089-6115 (2023) - [c4]Xin Zhang, Vishal Sharma, Yuncheng Lu, Yong-Jun Jo, Tony Tae-Hyoung Kim:
A 400MHz 249.1TOPS/W 64Kb Fully-Reconfigurable SRAM-Based Digital Compute-in-Memory Macro for Accelerating CNNs. A-SSCC 2023: 1-3 - 2022
- [j4]Vishal Sharma, Ju Eon Kim, Hyunjoon Kim, Lu Lu, Tony Tae-Hyoung Kim:
A Reconfigurable 16Kb AND8T SRAM Macro With Improved Linearity for Multibit Compute-In Memory of Artificial Intelligence Edge Devices. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(2): 522-535 (2022) - [j3]Vishal Sharma, Hyunjoon Kim, Tony Tae-Hyoung Kim:
A 64 Kb Reconfigurable Full-Precision Digital ReRAM-Based Compute-In-Memory for Artificial Intelligence Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 69(8): 3284-3296 (2022) - 2021
- [c3]Vishal Sharma, Ju Eon Kim, Yong-Jun Jo, Yuzong Chen, Tony Tae-Hyoung Kim:
AND8T SRAM Macro with Improved Linearity for Multi-Bit In-Memory Computing. ISCAS 2021: 1-5 - 2020
- [j2]Gopal Raut, Ambika Prasad Shah, Vishal Sharma, Gunjan Rajput, Santosh Kumar Vishvakarma:
A 2.4-GS/s Power-Efficient, High-Resolution Reconfigurable Dynamic Comparator for ADC Architecture. Circuits Syst. Signal Process. 39(9): 4681-4694 (2020) - [c2]Lu Lu, Ju Eon Kim, Vishal Sharma, Tony Tae-Hyoung Kim:
ReRAM Device and Circuit Co-Design Challenges in Nano-scale CMOS Technology. APCCAS 2020: 213-216
2010 – 2019
- 2018
- [j1]Vishal Sharma, Santosh Kumar Vishvakarma, Shailesh Singh Chouhan, Kari Halonen:
A write-improved low-power 12T SRAM cell for wearable wireless sensor nodes. Int. J. Circuit Theory Appl. 46(12): 2314-2333 (2018) - [c1]Vishal Sharma, Pranshu Bisht, Abhishek Dalal, Shailesh Singh Chouhan, H. S. Jattana, Santosh Kumar Vishvakarma:
A Write-Improved Half-Select-Free Low-Power 11T Subthreshold SRAM with Double Adjacent Error Correction for FPGA-LUT Design. VDAT 2018: 551-564
Coauthor Index
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