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Journal Articles
- 2024
[j13]Bolin Ren
, Fangxu Lv, Mingche Lai, Liquan Xiao, Geng Zhang, Xuqiang Zheng, Zhang Luo, Jiaqing Xu:
A 56-Gb/s,0.708 pJ/bit single-ended simultaneous bidirectional transceiver with hybrid errors cancellation techniques for die-to-die interface. Microelectron. J. 152: 106326 (2024)- [j12]Meng Li, Fangxu Lv, Mingche Lai, Xuqiang Zheng, Heng Huang, Xingyun Qi, Geng Zhang:
A fully digital timing background calibration algorithm based on first-order auto-correlation for time-interleaved ADCs. Microelectron. J. 152: 106330 (2024) - [j11]Zhang Luo, Sichun Du, Zedi Zhang, Fangxu Lv, Qinghui Hong, Mingche Lai:
Artificial Neural Network Based on Memristive Circuit for High-Speed Equalization. IEEE Trans. Circuits Syst. I Regul. Pap. 71(4): 1745-1756 (2024) - [j10]Kewei Xin, Mingche Lai, Fangxu Lv, Xuqiang Zheng, Kaile Guo, Zhengbin Pang, Chaolong Xu, Geng Zhang, Wenchen Wang, Meng Li:
Frequency Domain Modeling and Performance Analysis of Injection-Locked LC Oscillator. IEEE Trans. Circuits Syst. II Express Briefs 71(1): 11-15 (2024) - 2023
- [j9]Qiuyue Zhang, Xuqiang Zheng, Fangxu Lv, Zhaoyang Liu, Hua Xu, Weijie Li, Zhi Jin, Mingche Lai, Xinyu Liu:
A 50 Gb/s PAM-4 EAM driver in 28-nm CMOS technology. Microelectron. J. 140: 105905 (2023) - [j8]Bingxi Pei, Shi Xu, Zhang Luo, Qin Wang, Mingche Lai, Weifeng He:
A Unified Clock-Gated Error Correction Scheme With Three-Phase Latch-Based Pipeline for Energy-Efficient Wide Supply Voltage Range Router. IEEE Trans. Circuits Syst. II Express Briefs 70(10): 3787-3791 (2023) - 2022
- [j7]Geng Zhang, Mingche Lai, Fangxu Lyu, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi, Qing Liu:
A CNRZ-7 Based Wireline Transceiver With High-Bandwidth-Density, Low-Power for D2D Communication. IEEE Access 10: 96556-96567 (2022) - [j6]Bingxi Pei, Shi Xu, Zhang Luo, Qin Wang, Mingche Lai, Wei-Feng He:
Hierarchical photoelectric hybrid packet switching network for high-performance computing. JOCN 14(8): 680-690 (2022) - [j5]Mingche Lai, Geng Zhang, Fangxu Lv, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi:
A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS. Microelectron. J. 130: 105628 (2022) - 2020
- [j4]Shi Xu, Mingche Lai, Yi Dai, Jijun Cao, Kefei Wang:
A scalable smart router architecture with intelligent adaptive routing and fault-tolerant management. Neurocomputing 393: 126-141 (2020) - 2018
- [j3]Jie Jian, Mingche Lai, Liquan Xiao:
Optimize the Power Consumption and SNR of the 3D Photonic High-Radix Switch Architecture Based on Extra Channels and Redundant Rings. J. Comput. Networks Commun. 2018: 8074074:1-8074074:8 (2018) - [j2]Shi Xu, Zhang Luo, Mingche Lai, Zhengbin Pang, Renfa Li:
Integrated High-Speed Optical SerDes over 100GBd Based on Optical Time Division Multiplexing. ACM J. Emerg. Technol. Comput. Syst. 14(2): 27:1-27:16 (2018) - 2016
- [j1]Jie Jian, Mingche Lai, Liquan Xiao:
A Fast Hierarchical Arbitration in Optical Network-on-Chip Based on Multi-Level Priority QoS. IEICE Trans. Commun. 99-B(4): 875-884 (2016)
Conference and Workshop Papers
- 2024
- [c15]Yu He, Xuqiang Zhenq, Zedong Wang, Zunsong Yanq, Hua Xu, Fangxu Lv, Mingche Lai, Xinyu Liu:
An Injection-Locked Clock Multiplier with Adaptive Pulsewidth Adjustment and Phase Error Cancellation Achieving 43.9fs RMS Jitter and -255.5dB FoM. CICC 2024: 1-2 - [c14]Haoyu Liao, Yuan Li, Puguang Liu, Qiang Wang, Mingche Lai, Xingyun Qi:
Optimization of TDM Using Single-ended Transmission for Multi-FPGA Platforms. ISCAS 2024: 1-5 - 2023
- [c13]Mingche Lai, Fangxu Lv, Geng Zhang, Chaolong Xu:
A Low BER Cooperative-adaptive-equalizer for Serial Receiver in HPC Networks. HPCC/DSS/SmartCity/DependSys 2023: 742-749 - [c12]Lin Shao, Mingche Lai, Shi Xu, Chuxiong Lin, Weifeng He:
A Metastability Inference and Avoidance Technique for Near-Threshold-Voltage Network-on-Chip. ISCAS 2023: 1-5 - 2022
- [c11]Jijun Cao, Mingche Lai, Lu Liu, Jiaqing Xu, Xiaoyue Hu:
In-Band Management Framework and Performance Evaluation for Interconnect Network in the TianHe Exascale Prototype System. HPCC/DSS/SmartCity/DependSys 2022: 438-445 - 2021
- [c10]Xingyun Qi, Mingche Lai, Dezun Dong, Yi Dai, Junsheng Chang, Jijun Cao:
PFT: A Congestion Avoidance Method based on Proactive Flow Throttling at Endpoints. IM 2021: 572-578 - 2020
- [c9]Jijun Cao, Mingche Lai, Xingyun Qi, Yi Dai, Zhengbin Pang:
Optimal Implementation of In-Band Network Management for High-Radix Switches. ACA 2020: 16-30 - [c8]Zhengbin Pang, Fangxu Lv, Weiping Tang, Mingche Lai, Kaile Guo, Yuxuan Wu, Tao Liu, Miaomiao Wu, Dechao Lu:
A 32 Gb/s Low Power Little Area Re-timer with PI Based CDR in 65 nm CMOS Technology. ACA 2020: 31-42 - [c7]Xingyun Qi, Pingjing Lu, Jijun Cao, Yi Dai, Mingche Lai, Junsheng Chang:
MPLEG: A Multi-mode Physical Layer Error Generator for Link Layer Fault Tolerance Test. ACA 2020: 56-69 - [c6]Chao Wang, Weixia Xu, Mingche Lai, Jijun Cao:
Design of Converged Network Coding Layer for the Ethernet and HPC High-Speed Network. HPCC/DSS/SmartCity 2020: 163-169 - 2019
- [c5]Yi Dai, Ke Wu, Mingche Lai, Qiong Li, Dezun Dong:
PPS: A Low-Latency and Low-Complexity Switching Architecture Based on Packet Prefetch and Arbitration Prediction. ICA3PP (1) 2019: 3-16 - [c4]Jijun Cao, Mingche Lai, Zhang Luo, Jiaqing Xu, Zhengbin Pang:
Efficient Management and Intelligent Fault Tolerance for HPC Interconnect Networks. ICPADS 2019: 343-351 - 2016
- [c3]Jie Jian, Mingche Lai, Liquan Xiao, Weixia Xu:
Graphein: A Novel Optical High-Radix Switch Architecture for 3D Integration. ICA3PP 2016: 162-177 - [c2]Jie Jian, Liquan Xiao, Mingche Lai, Shi Xu:
A High-Radix Switch Architecture Based on Silicon Photonic and 3D Integration. NCCET 2016: 179-190 - 2015
- [c1]Jie Jian, Mingche Lai, Liquan Xiao:
A Low-Latency and High-Throughput Multiple-Level Arbitration Scheme Supporting Quality-of-Service in Optical On-chip Network. NoCArc@MICRO 2015: 9-14
Coauthor Index
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