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ORCIDGeng Zhang 0001
Person information
- affiliation: National University of Defense Technology, College of Computer Science and Technology, Changsha, China
- affiliation: Air Force Engineering University, School of Air and Missile Defense College, Xi'an, China
Other persons with the same name
- Geng Zhang — disambiguation page
- Geng Zhang 0002
![[0000-0001-8898-4355]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0001-8898-4355")
— National University of Singapore, Singapore (and 1 more)
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Journal Articles
- 2025
[j7]Chaolong Xu, Fangxu Lv, Mingche Lai, Xingyun Qi, Qiang Wang, Zhang Luo, Shijie Li, Geng Zhang:
A Novel High-Speed Adaptive Duobinary Digital Detector Based on the Feed-Forward Equalizer and the Maximum Likelihood Sequence Detector for Wireline Transceivers. IEEE Trans. Very Large Scale Integr. Syst. 33(4): 1042-1052 (2025)- 2024
- [j6]Wenchen Wang, Fangxu Lv, Zhengbin Pang, Heng Huang, Zhang Luo, Xingyun Qi, Jiaqing Xu, Geng Zhang, Kewei Xin, Chengzhuo Zhao:
A low jitter and low reference spur 5GHz PLL with quadrature charge-sampling PD in 28nm CMOS process. IEICE Electron. Express 21(19): 20240375 (2024) - [j5]Bolin Ren, Fangxu Lv, Mingche Lai, Liquan Xiao, Geng Zhang, Xuqiang Zheng, Zhang Luo, Jiaqing Xu:
A 56-Gb/s,0.708 pJ/bit single-ended simultaneous bidirectional transceiver with hybrid errors cancellation techniques for die-to-die interface. Microelectron. J. 152: 106326 (2024) - [j4]Meng Li, Fangxu Lv, Mingche Lai, Xuqiang Zheng, Heng Huang, Xingyun Qi, Geng Zhang:
A fully digital timing background calibration algorithm based on first-order auto-correlation for time-interleaved ADCs. Microelectron. J. 152: 106330 (2024) - [j3]Kewei Xin, Mingche Lai, Fangxu Lv, Xuqiang Zheng, Kaile Guo, Zhengbin Pang, Chaolong Xu, Geng Zhang, Wenchen Wang, Meng Li:
Frequency Domain Modeling and Performance Analysis of Injection-Locked LC Oscillator. IEEE Trans. Circuits Syst. II Express Briefs 71(1): 11-15 (2024) - 2022
- [j2]Geng Zhang, Mingche Lai, Fangxu Lyu, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi, Qing Liu:
A CNRZ-7 Based Wireline Transceiver With High-Bandwidth-Density, Low-Power for D2D Communication. IEEE Access 10: 96556-96567 (2022) - [j1]Mingche Lai, Geng Zhang, Fangxu Lv, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi:
A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS. Microelectron. J. 130: 105628 (2022)
Conference and Workshop Papers
- 2023
- [c3]Mingche Lai, Fangxu Lv, Geng Zhang, Chaolong Xu:
A Low BER Cooperative-adaptive-equalizer for Serial Receiver in HPC Networks. HPCC/DSS/SmartCity/DependSys 2023: 742-749 - [c2]Qing Liu, Heming Wang, Fangxu Lv, Geng Zhang, Dongbin Lv:
Low-Jitter Retimer Circuits for High-Performance Computer Optical Communications. ICCEIC 2023: 216-220 - 2021
- [c1]Geng Zhang, Fangxu Lv, Zhengbin Pang, Heming Wang, Dongbin Lv, Tao Liu, Jinwang Zhang:
A 5-156.25Gb/s high pin efficiency Receiver Based on CNRZ-5 for USR High-Speed Interface. ASICON 2021: 1-4
Coauthor Index
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