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Journal Articles
- 2012
[j7]Ramin Farjad-Rad, Friedel Gerfers, Michael Brown, Ahmad Tavakoli, David Nguyen, Hossein Sedarat, Ramin Shirani, Hiok-Tiaq Ng:
A 48-Port FCC-Compliant 10GBASE-T Transmitter With Mixed-Mode Adaptive Echo Canceller. IEEE J. Solid State Circuits 47(12): 3261-3272 (2012)- 2004
- [j6]Ramin Farjad-Rad, Anhtuyet Nguyen, James Tran, Trey Greer, John Poulton, William J. Dally, John H. Edmondson, Ramesh Senthinathan, Rohit Rathi, Ming-Ju Edward Lee, Hiok-Tiaq Ng:
A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os. IEEE J. Solid State Circuits 39(9): 1553-1561 (2004) - 2003
- [j5]Ming-Ju Edward Lee, William J. Dally, Trey Greer, Hiok-Tiaq Ng, Ramin Farjad-Rad, John Poulton, Ramesh Senthinathan:
Jitter transfer characteristics of delay-locked loops - theories and design techniques. IEEE J. Solid State Circuits 38(4): 614-621 (2003) - [j4]Hiok-Tiaq Ng, Ramin Farjad-Rad, Ming-Ju Edward Lee, William J. Dally, Trey Greer, John Poulton, John H. Edmondson, Rohit Rathi, Ramesh Senthinathan:
A second-order semidigital clock recovery circuit based on injection locking. IEEE J. Solid State Circuits 38(12): 2101-2110 (2003) - 2002
- [j3]Ramin Farjad-Rad, William J. Dally, Hiok-Tiaq Ng, Ramesh Senthinathan, Ming-Ju Edward Lee, Rohit Rathi, John Poulton:
A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips. IEEE J. Solid State Circuits 37(12): 1804-1812 (2002) - 1999
- [j2]Hiok-Tiaq Ng, Ramsin M. Ziazadeh, David J. Allstot:
A multistage amplifier technique with embedded frequency compensation. IEEE J. Solid State Circuits 34(3): 339-347 (1999) - 1997
- [j1]Hiok-Tiaq Ng, David J. Allstot:
CMOS current steering logic for low-voltage mixed-signal integrated circuits. IEEE Trans. Very Large Scale Integr. Syst. 5(3): 301-308 (1997)
Conference and Workshop Papers
- 2012
- [c5]Friedel Gerfers, Ramin Farjad-Rad, Michael Brown, Ahmad Tavakoli, David Nguyen, Hiok-Tiaq Ng, Ramin Shirani:
A 16-port FCC-compliant 10GBase-T transmitter and hybrid with 76dBc SFDR up to 400MHz scalable to 48 ports. ISSCC 2012: 412-413 - 2003
- [c4]Hiok-Tiaq Ng, Ming-Ju Edward Lee, Ramin Farjad-Rad, Ramesh Senthinathan, William J. Dally, Anhtuyet Nguyen, Rohit Rathi, Trey Greer, John Poulton, John H. Edmondson, James Tran:
A 33mW 8Gb/s CMOS clock multiplier and CDR for highly integrated I/Os. CICC 2003: 77-80 - [c3]Ming-Ju Edward Lee, William J. Dally, Ramin Farjad-Rad, Hiok-Tiaq Ng, Ramesh Senthinathan, John H. Edmondson, John W. Poulton:
CMOS High-Speed I/Os - Present and Future. ICCD 2003: 454-461 - 1998
- [c2]Ramsin M. Ziazadeh, Hiok-Tiaq Ng, David J. Allstot:
A multistage amplifier topology with embedded tracking compensation. CICC 1998: 361-364 - 1997
- [c1]Jianjun Zhou, Ramsin M. Ziazadeh, H.-H. Ng, Hiok-Tiaq Ng, David J. Allstot:
Charge-pump assisted low-power/low-voltage CMOS opamp design. ISLPED 1997: 108-109
Coauthor Index
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