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Nian-Ze Lee
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Journal Articles
- 2024
- [j4]Dirk Beyer, Po-Chun Chien, Marek Jankola, Nian-Ze Lee:
A Transferability Study of Interpolation-Based Hardware Model Checking for Software Verification. Proc. ACM Softw. Eng. 1(FSE): 2028-2050 (2024) - [j3]Marie-Christine Jakobs, Nian-Ze Lee:
Summary of the Eighth International Workshop on CPAchecker(CPAchecker 2023). ACM SIGSOFT Softw. Eng. Notes 49(2): 25-26 (2024) - 2021
- [j2]Nian-Ze Lee, Jie-Hong R. Jiang:
Constraint Solving for Synthesis and Verification of Threshold Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(5): 904-917 (2021) - 2018
- [j1]Nian-Ze Lee, Jie-Hong R. Jiang:
Towards Formal Evaluation and Verification of Probabilistic Design. IEEE Trans. Computers 67(8): 1202-1216 (2018)
Conference and Workshop Papers
- 2024
- [c20]Daniel Baier, Dirk Beyer, Po-Chun Chien, Marie-Christine Jakobs, Marek Jankola, Matthias Kettl, Nian-Ze Lee, Thomas Lemberger, Marian Lingsch Rosenfeld, Henrik Wachowitz, Philipp Wendler:
Software Verification with CPAchecker 3.0: Tutorial and User Guide. FM (2) 2024: 543-570 - [c19]Zsófia Ádám, Dirk Beyer, Po-Chun Chien, Nian-Ze Lee, Nils Sirrenberg:
Btor2-Cert: A Certifying Hardware-Verification Framework Using Software Analyzers. TACAS (3) 2024: 129-149 - [c18]Daniel Baier, Dirk Beyer, Po-Chun Chien, Marek Jankola, Matthias Kettl, Nian-Ze Lee, Thomas Lemberger, Marian Lingsch Rosenfeld, Martin Spiessl, Henrik Wachowitz, Philipp Wendler:
CPAchecker 2.3 with Strategy Selection - (Competition Contribution). TACAS (3) 2024: 359-364 - [c17]Po-Chun Chien, Nian-Ze Lee:
CPV: A Circuit-Based Program Verifier. TACAS (3) 2024: 365-370 - 2023
- [c16]Dirk Beyer, Po-Chun Chien, Nian-Ze Lee:
CPA-DF: A Tool for Configurable Interval Analysis to Boost Program Verification. ASE 2023: 2050-2053 - [c15]Dirk Beyer, Po-Chun Chien, Nian-Ze Lee:
Bridging Hardware and Software Analysis with Btor2C: A Word-Level-Circuit-to-C Translator. TACAS (2) 2023: 152-172 - 2021
- [c14]Nian-Ze Lee, Jie-Hong R. Jiang:
Dependency Stochastic Boolean Satisfiability: A Logical Formalism for NEXPTIME Decision Problems with Uncertainty. AAAI 2021: 3877-3885 - 2020
- [c13]Jie-Hong R. Jiang, Victor N. Kravets, Nian-Ze Lee:
Engineering Change Order for Combinational and Sequential Design Rectification. DATE 2020: 726-731 - 2019
- [c12]Victor N. Kravets, Nian-Ze Lee, Jie-Hong R. Jiang:
Comprehensive Search for ECO Rectification Using Symbolic Sampling. DAC 2019: 71 - [c11]Nian-Ze Lee, Paolo Arcaini, Shaukat Ali, Fuyuki Ishikawa:
Stability analysis for safety of automotive multi-product lines: a search-based approach. GECCO 2019: 1241-1249 - [c10]Siang-Yun Lee, Nian-Ze Lee, Jie-Hong R. Jiang:
Searching Parallel Separating Hyperplanes for Effective Compression of Threshold Logic Networks. ICCAD 2019: 1-8 - [c9]Akihisa Yamada, Clovis Eberhart, Fuyuki Ishikawa, Nian-Ze Lee:
Scenario Sampling for Cyber Physical Systems using Combinatorial Testing. ICST Workshops 2019: 198-199 - [c8]Shaukat Ali, Paolo Arcaini, Ichiro Hasuo, Fuyuki Ishikawa, Nian-Ze Lee:
Towards a Framework for the Analysis of Multi-Product Lines in the Automotive Domain. VaMoS 2019: 12:1-12:6 - 2018
- [c7]Ai Quoc Dao, Nian-Ze Lee, Li-Cheng Chen, Mark Po-Hung Lin, Jie-Hong R. Jiang, Alan Mishchenko, Robert K. Brayton:
Efficient computation of ECO patch functions. DAC 2018: 51:1-51:6 - [c6]Siang-Yun Lee, Nian-Ze Lee, Jie-Hong R. Jiang:
Canonicalization of threshold logic representation and its applications. ICCAD 2018: 85 - [c5]Nian-Ze Lee, Yen-Shi Wang, Jie-Hong R. Jiang:
Solving Exist-Random Quantified Stochastic Boolean Satisfiability via Clause Selection. IJCAI 2018: 1339-1345 - 2017
- [c4]Nian-Ze Lee, Victor N. Kravets, Jie-Hong R. Jiang:
Sequential engineering change order under retiming and resynthesis. ICCAD 2017: 109-116 - [c3]Nian-Ze Lee, Yen-Shi Wang, Jie-Hong R. Jiang:
Solving Stochastic Boolean Satisfiability under Random-Exist Quantification. IJCAI 2017: 688-694 - 2016
- [c2]Nian-Ze Lee, Hao-Yuan Kuo, Yi-Hsiang Lai, Jie-Hong R. Jiang:
Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits. ICCAD 2016: 5 - 2014
- [c1]Nian-Ze Lee, Jie-Hong R. Jiang:
Towards formal evaluation and verification of probabilistic design. ICCAD 2014: 340-347
Data and Artifacts
- 2020
- [d1]Dirk Beyer, Nian-Ze Lee, Philipp Wendler:
Reproduction Package for TACAS 2021 Submission 'Interpolation and SAT-Based Model Checking Revisited'. Zenodo, 2020
Informal and Other Publications
- 2024
- [i4]Dirk Beyer, Po-Chun Chien, Nian-Ze Lee:
Augmenting Interpolation-Based Model Checking with Auxiliary Invariants (Extended Version). CoRR abs/2403.07821 (2024) - [i3]Salih Ates, Dirk Beyer, Po-Chun Chien, Nian-Ze Lee:
MoXIchecker: An Extensible Model Checker for MoXI. CoRR abs/2407.15551 (2024) - 2022
- [i2]Dirk Beyer, Nian-Ze Lee, Philipp Wendler:
Interpolation and SAT-Based Model Checking Revisited: Adoption to Software Verification. CoRR abs/2208.05046 (2022) - 2019
- [i1]Nian-Ze Lee, Jie-Hong R. Jiang:
Dependency Stochastic Boolean Satisfiability: A Logical Formalism for NEXPTIME Decision Problems with Uncertainty. CoRR abs/1911.04112 (2019)
Coauthor Index
aka: Jie-Hong R. Jiang
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