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Siddhartha 0001
Person information
- affiliation: Advanced Micro Devices, Singapore
- affiliation (PhD 2019): Nanyang Technological University, Singapore
Other persons with the same name
- Siddhartha 0002 — PricewaterhouseCoopers Pvt. Ltd., Mumbai, India
- Siddhartha 0003 — University of Sydney, Australia
- Siddhartha 0004 — Indian Institute of Space Science and Technology, Trivandrum, India
- Siddhartha 0005 — Saarland University, Saarbrücken, Germany
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2020 – today
- 2023
- [c14]Siddhartha, Justin Tan, Rajesh Bansal, Huang Chee Cheun, Yuta Tokusashi, Chong Yew Kwan, Haris Javaid, Mario Baldi:
Demo: Enabling DNN Inference in the Network Data Plane. EuroP4@CoNEXT 2023: 65-68 - 2020
- [c13]Weichong Ng, Guohua Wang, Siddhartha, Zhiping Lin, Bhaskar Jyoti Dutta:
Range-Doppler Detection in Automotive Radar with Deep Learning. IJCNN 2020: 1-8
2010 – 2019
- 2019
- [b1]Siddhartha:
Dataflow optimized overlays for FPGAs. Nanyang Technological University, Singapore, 2019 - 2018
- [j1]Gopalakrishna Hegde, Siddhartha, Nachiket Kapre:
CaffePresso: Accelerating Convolutional Networks on Embedded SoCs. ACM Trans. Embed. Comput. Syst. 17(1): 15:1-15:26 (2018) - [c12]Siddhartha, Nachiket Kapre:
Hoplite-Q: Priority-Aware Routing in FPGA Overlay NoCs. FCCM 2018: 17-24 - [c11]Siddhartha, Nachiket Kapre:
DaCO: A High-Performance Token Dataflow Coprocessor Overlay for FPGAs. FPT 2018: 158-165 - 2017
- [c10]Siddhartha, Nachiket Kapre:
eBSP: Managing NoC traffic for BSP workloads on the 16-core Adapteva Epiphany-III processor. DATE 2017: 73-78 - [i1]Siddhartha, Nachiket Kapre:
Out-of-Order Dataflow Scheduling for FPGA Overlays. CoRR abs/1705.02734 (2017) - 2016
- [c9]Gopalakrishna Hegde, Siddhartha, Nachiappan Ramasamy, Nachiket Kapre:
CaffePresso: an optimized library for deep learning on embedded accelerator-based platforms. CASES 2016: 14:1-14:10 - [c8]Gopalakrishna Hegde, Siddhartha, Nachiappan Ramasamy, Vamsi Buddha, Nachiket Kapre:
Evaluating Embedded FPGA Accelerators for Deep Learning Applications. FCCM 2016: 25 - [c7]Nachiket Kapre, Siddhartha:
Communication Optimization for the 16-Core Epiphany Floating-Point Processor Array. FCCM 2016: 26 - [c6]Sidharth Maheshwari, Gourav Modi, Siddhartha, Nachiket Kapre:
Vector FPGA acceleration of 1-D DWT computations using sparse matrix skeletons. FPL 2016: 1-4 - 2015
- [c5]Siddhartha, Nachiket Kapre:
FPGA Acceleration of Irregular Iterative Computations using Criticality-Aware Dataflow Optimizations (Abstract Only). FPGA 2015: 277 - [c4]Nachiket Kapre, Han Jianglei, Andrew Bean, Pradeep Moorthy, Siddhartha:
GraphMMU: Memory Management Unit for Sparse Graph Accelerators. IPDPS Workshops 2015: 113-120 - 2014
- [c3]Siddhartha, Nachiket Kapre:
Breaking Sequential Dependencies in FPGA-Based Sparse LU Factorization. FCCM 2014: 60-63 - [c2]Siddhartha, Nachiket Kapre:
Heterogeneous dataflow architectures for FPGA-based sparse LU factorization. FPL 2014: 1-4 - [c1]Siddhartha, Nachiket Kapre:
Fanout decomposition dataflow optimizations for FPGA-based Sparse LU factorization. FPT 2014: 252-255
Coauthor Index
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