![](https://dblp.uni-trier.de/img/logo.ua.320x120.png)
![](https://dblp.uni-trier.de/img/dropdown.dark.16x16.png)
![](https://dblp.uni-trier.de/img/peace.dark.16x16.png)
Остановите войну!
for scientists:
![search dblp search dblp](https://dblp.uni-trier.de/img/search.dark.16x16.png)
![search dblp](https://dblp.uni-trier.de/img/search.dark.16x16.png)
default search action
"Coarse Grained FPGA Overlay for Rapid Just-In-Time Accelerator Compilation."
Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy (2022)
- Abhishek Kumar Jain
, Douglas L. Maskell
, Suhaib A. Fahmy
:
Coarse Grained FPGA Overlay for Rapid Just-In-Time Accelerator Compilation. IEEE Trans. Parallel Distributed Syst. 33(6): 1478-1490 (2022)
![](https://dblp.uni-trier.de/img/cog.dark.24x24.png)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.