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Journal Articles
- 2020
[j5]Kyung-Soo Ha
, Seungseob Lee, Youn-Sik Park, Hyuck-Joon Kwon, Tae-Young Oh, Young-Soo Sohn, Seung-Jun Bae, Kwang-Il Park, Jung-Bae Lee, Chang-Kyo Lee, Dongkeon Lee, Daesik Moon, Hyong-Ryol Hwang, Dukha Park, Young-Hwa Kim, Young Hoon Son, Byongwook Na:
A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques. IEEE J. Solid State Circuits 55(1): 157-166 (2020)- 2018
- [j4]Sukhan Lee, Hyunyoon Cho, Young Hoon Son, Yuhwan Ro, Nam Sung Kim, Jung Ho Ahn:
Leveraging Power-Performance Relationship of Energy-Efficient Modern DRAM Devices. IEEE Access 6: 31387-31398 (2018) - 2017
- [j3]Young Hoon Son, Hyunyoon Cho, Yuhwan Ro, Jae W. Lee, Jung Ho Ahn:
SALAD: Achieving Symmetric Access Latency with Asymmetric DRAM Architecture. IEEE Comput. Archit. Lett. 16(1): 76-79 (2017) - 2015
- [j2]Seongil O, Sanghyuk Kwon, Young Hoon Son, Yujin Park, Jung Ho Ahn:
CIDR: A Cache Inspired Area-Efficient DRAM Resilience Architecture against Permanent Faults. IEEE Comput. Archit. Lett. 14(1): 17-20 (2015) - 2013
- [j1]Jung Ho Ahn, Young Hoon Son, John Kim:
Scalable high-radix router microarchitecture using a network switch organization. ACM Trans. Archit. Code Optim. 10(3): 17:1-17:25 (2013)
Conference and Workshop Papers
- 2021
- [c12]Seunghak Lee, Ki-Dong Kang, Hwanjun Lee, Hyungwon Park, Young Hoon Son, Nam Sung Kim, Daehoon Kim:
GreenDIMM: OS-assisted DRAM Power Management for DRAM with a Sub-array Granularity Power-Down State. MICRO 2021: 131-142 - 2017
- [c11]Chang-Kyo Lee, Junha Lee, Kiho Kim, Jin-Seok Heo, Gil-Hoon Cha, Jin-Hyeok Baek, Daesik Moon, Yoon-Joo Eom, Tae-Sung Kim, Hyunyoon Cho, Young Hoon Son, Seonghwan Kim, Jong-Wook Park, Sewon Eom, Si-Hyeong Cho, Young-Ryeol Choi, Seungseob Lee, Kyoung-Soo Ha, Youngseok Kim, Bo-Tak Lim, Dae-Hee Jung, Eungsung Seo, Kyoung-Ho Kim, Yoon-Gyu Song, Youn-Sik Park, Tae-Young Oh, Seung-Jun Bae, Indal Song, Seok-Hun Hyun, Joon-Young Park, Hyuck-Joon Kwon, Young-Soo Sohn, Jung-Hwan Choi, Kwang-Il Park, Seong-Jin Jang:
Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM. A-SSCC 2017: 153-156 - [c10]Sang-uhn Cha, Seongil O, Hyunsung Shin, Sangjoon Hwang, Kwang-Il Park, Seong-Jin Jang, Joo-Sun Choi, Gyo-Young Jin, Young Hoon Son, Hyunyoon Cho, Jung Ho Ahn, Nam Sung Kim:
Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices. HPCA 2017: 61-72 - [c9]Yuhwan Ro, Hyunyoon Cho, Eojin Lee, Daejin Jung, Young Hoon Son, Jung Ho Ahn, Jae W. Lee:
SOUP-N-SALAD: Allocation-Oblivious Access Latency Reduction with Asymmetric DRAM Microarchitectures. HPCA 2017: 517-528 - [c8]Sukhan Lee, Yuhwan Ro, Young Hoon Son, Hyunyoon Cho, Nam Sung Kim, Jung Ho Ahn:
Understanding power-performance relationship of energy-efficient modern DRAM devices. IISWC 2017: 110-111 - 2016
- [c7]Hadi Asghari Moghaddam, Young Hoon Son, Jung Ho Ahn, Nam Sung Kim:
Chameleon: Versatile and practical near-DRAM acceleration architecture for large memory systems. MICRO 2016: 50:1-50:13 - 2015
- [c6]Young Hoon Son, Sukhan Lee, Seongil O, Sanghyuk Kwon, Nam Sung Kim, Jung Ho Ahn:
CiDRA: A cache-inspired DRAM resilience architecture. HPCA 2015: 502-513 - 2014
- [c5]Seongil O, Young Hoon Son, Nam Sung Kim, Jung Ho Ahn:
Row-buffer decoupling: A case for low-latency DRAM microarchitecture. ISCA 2014: 337-348 - [c4]Young Hoon Son, Seongil O, Hyunggyun Yang, Daejin Jung, Jung Ho Ahn, John Kim, Jangwoo Kim, Jae W. Lee:
Microbank: Architecting Through-Silicon Interposer-Based Main Memory Systems. SC 2014: 1059-1070 - 2013
- [c3]Daniel W. Chang, Young Hoon Son, Jung Ho Ahn, Hoyoung Kim, Minwook Ahn, Michael J. Schulte, Nam Sung Kim:
Dynamic bandwidth scaling for embedded DSPs with 3D-stacked DRAM and wide I/Os. ICCAD 2013: 747-754 - [c2]Young Hoon Son, Seongil O, Yuhwan Ro, Jae W. Lee, Jung Ho Ahn:
Reducing memory access latency with asymmetric DRAM bank organizations. ISCA 2013: 380-391 - 2012
- [c1]Yong-Cheol Bae, Joon-Young Park, Sang Jae Rhee, Seung-Bum Ko, Yonggwon Jeong, Kwang-Sook Noh, Young Hoon Son, Jaeyoun Youn, Yonggyu Chu, Hyunyoon Cho, Mijo Kim, Daesik Yim, Hyo-Chang Kim, Sang-Hoon Jung, Hye-In Choi, Sungmin Yim, Jung-Bae Lee, Joo-Sun Choi, Kyungseok Oh:
A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme. ISSCC 2012: 44-46
Coauthor Index
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