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Journal Articles
- 2019
[j4]Weicheng Liu, Can Sitik
, Emre Salman, Baris Taskin, Savithri Sundareswaran, Benjamin Huang:
SLECTS: Slew-Driven Clock Tree Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 27(4): 864-874 (2019)- 2016
- [j3]Can Sitik, Weicheng Liu, Baris Taskin, Emre Salman:
Design Methodology for Voltage-Scaled Clock Distribution Networks. IEEE Trans. Very Large Scale Integr. Syst. 24(10): 3080-3093 (2016) - 2015
- [j2]Can Sitik, Emre Salman, Leo Filippini, Sung-Jun Yoon, Baris Taskin:
FinFET-Based Low-Swing Clocking. ACM J. Emerg. Technol. Comput. Syst. 12(2): 13:1-13:20 (2015) - 2014
- [j1]Can Sitik, Baris Taskin:
Iterative skew minimization for low swing clocks. Integr. 47(3): 356-364 (2014)
Conference and Workshop Papers
- 2019
- [c11]Can Sitik, Weicheng Liu, Baris Taskin, Emre Salman:
Low Voltage Clock Tree Synthesis with Local Gate Clusters. ACM Great Lakes Symposium on VLSI 2019: 99-104 - 2016
- [c10]Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin:
Exploiting useful skew in gated low voltage clock trees. ISCAS 2016: 2595-2598 - 2015
- [c9]Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin:
Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks. ACM Great Lakes Symposium on VLSI 2015: 283-288 - [c8]Mallika Rathore, Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin:
A Novel Static D-Flip-Flop Topology for Low Swing Clocking. ACM Great Lakes Symposium on VLSI 2015: 301-306 - [c7]Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin:
Enhanced level shifter for multi-voltage operation. ISCAS 2015: 1442-1445 - 2014
- [c6]Can Sitik, Scott Lerner, Baris Taskin:
Timing characterization of clock buffers for clock tree synthesis. ICCD 2014: 230-236 - [c5]Can Sitik, Leo Filippini, Emre Salman, Baris Taskin:
High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design. ISVLSI 2014: 498-503 - 2013
- [c4]Can Sitik, Baris Taskin:
Skew-bounded low swing clock tree optimization. ACM Great Lakes Symposium on VLSI 2013: 49-54 - [c3]Can Sitik, Baris Taskin:
Multi-corner multi-voltage domain clock mesh design. ACM Great Lakes Symposium on VLSI 2013: 209-214 - [c2]Can Sitik, Prawat Nagvajara, Baris Taskin:
A microcontroller-based embedded system design course with PSoC3. MSE 2013: 28-31 - 2012
- [c1]Can Sitik, Baris Taskin:
Multi-voltage domain clock mesh design. ICCD 2012: 201-206
Coauthor Index
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