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ORCIDPrzemyslaw Mroszczyk
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2010 – 2019
- 2019
[j3]Przemyslaw Mroszczyk
, John Goodacre, Vasilis F. Pavlidis:
Energy Efficient Flash ADC With PVT Variability Compensation Through Advanced Body Biasing. IEEE Trans. Circuits Syst. II Express Briefs 66-II(11): 1775-1779 (2019)- [c8]Eleni Maragkoudaki, Przemyslaw Mroszczyk, Vasilis F. Pavlidis:
Adaptive Word Reordering for Low-Power Inter-Chip Communication. DATE 2019: 980-983 - 2018
- [c7]Przemyslaw Mroszczyk, Vasilis F. Pavlidis:
Mismatch Compensation Technique for Inverter-Based CMOS Circuits. ISCAS 2018: 1-5 - [c6]Przemyslaw Mroszczyk, Vasilis F. Pavlidis:
Ultra-low swing CMOS transceiver for 2.5-D integrated systems. ISQED 2018: 262-267 - [c5]Eleni Maragkoudaki, Przemyslaw Mroszczyk, Vasilis F. Pavlidis:
Energy Efficiency of Low Swing Signaling for Emerging Interposer Technologies. NANOARCH 2018: 124-130 - 2015
- [j2]Przemyslaw Mroszczyk, Piotr Dudek:
Trigger-Wave Asynchronous Cellular Logic Array for Fast Binary Image Processing. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(2): 497-506 (2015) - 2014
- [j1]Przemyslaw Mroszczyk, Piotr Dudek:
Tunable CMOS Delay Gate With Improved Matching Properties. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(9): 2586-2595 (2014) - [c4]Przemyslaw Mroszczyk, Piotr Dudek:
The accuracy and scalability of continuous-time Bayesian inference in analogue CMOS circuits. ISCAS 2014: 1576-1579 - 2013
- [c3]Przemyslaw Mroszczyk, Piotr Dudek:
Trigger-wave propagation in arbitrary metrics in asynchronous cellular logic arrays. ECCTD 2013: 1-4 - [c2]Przemyslaw Mroszczyk, Piotr Dudek:
Tunable CMOS delay gate with reduced impact of fabrication mismatch on timing parameters. NEWCAS 2013: 1-4 - 2012
- [c1]Przemyslaw Mroszczyk, Piotr Dudek:
Trigger-wave collision detecting asynchronous cellular logic array for fast image skeletonization. ISCAS 2012: 2653-2656
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