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ORCIDBalaram Sinharoy
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Journal Articles
- 2015
[j18]Balaram Sinharoy, James Van Norstrand, Richard J. Eickemeyer, Hung Q. Le, Jens Leenstra, Dung Q. Nguyen, B. Konigsburg, K. Ward, M. D. Brown, José E. Moreira, D. Levitan, S. Tung, David Hrusecky, James W. Bishop, Michael Gschwind, Maarten Boersma, Michael Kroener, Markus Kaltenbach, Tejas Karkhanis, K. M. Fernsler:
IBM POWER8 processor core microarchitecture. IBM J. Res. Dev. 59(1) (2015)- [j17]Balaram Sinharoy, Randal C. Swanberg, Naresh Nayar, Bruce G. Mealey, Jeffrey Stuecheli, Berni Schiefer, Jens Leenstra, Joefon Jann, P. Oehler, D. Levitan, S. Eisen, D. Sanner, Thomas Pflueger, Cédric Lichtenau, W. E. Hall, T. Block:
Advanced features in IBM POWER8 systems. IBM J. Res. Dev. 59(1) (2015) - 2011
- [j16]Dieter F. Wendel, Ronald N. Kalla, James D. Warnock, Robert Cargnoni, Sam G. Chu, Joachim G. Clabes, Daniel Dreps, David Hrusecky, Joshua Friedrich, Md. Saiful Islam, James A. Kahle, Jens Leenstra, Gaurav Mittal, Jose Paredes, Juergen Pille, Phillip J. Restle, Balaram Sinharoy, George Smith, William J. Starke, Scott A. Taylor, James Van Norstrand, Stephen Weitzel, Phillip G. Williams, Victor V. Zyuban:
POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor. IEEE J. Solid State Circuits 46(1): 145-161 (2011) - 2010
- [j15]Ronald N. Kalla, Balaram Sinharoy, William J. Starke, Michael S. Floyd:
Power7: IBM's Next-Generation Server Processor. IEEE Micro 30(2): 7-15 (2010) - 2005
- [j14]Balaram Sinharoy, Ronald N. Kalla, Joel M. Tendler, Richard J. Eickemeyer, Jody B. Joyner:
POWER5 system microarchitecture. IBM J. Res. Dev. 49(4-5): 505-522 (2005) - 2004
- [j13]Ronald N. Kalla, Balaram Sinharoy, Joel M. Tendler:
IBM Power5 Chip: A Dual-Core Multithreaded Processor. IEEE Micro 24(2): 40-47 (2004) - 2002
- [j12]Joel M. Tendler, J. Steve Dodson, J. S. Fields Jr., Hung Q. Le, Balaram Sinharoy:
POWER4 system microarchitecture. IBM J. Res. Dev. 46(1): 5-26 (2002) - 1999
- [j11]Balaram Sinharoy:
Compiler optimization to improve data locality for processor multithreading. Sci. Program. 7(1): 21-37 (1999) - 1997
- [j10]Balaram Sinharoy:
Optimized Thread Creation for Processor Multithreading. Comput. J. 40(6): 388-400 (1997) - [j9]Balaram Sinharoy, Boleslaw K. Szymanski:
Introduction: Special Issue on Optimising Compilers for Parallel Languages. Parallel Algorithms Appl. 12(1-3): 1-4 (1997) - [j8]Balaram Sinharoy, Boleslaw K. Szymanski:
Parallelising Compilers and Systems. Parallel Algorithms Appl. 12(1-3): 5-20 (1997) - 1995
- [j7]Balaram Sinharoy, Boleslaw K. Szymanski:
Announcement of a Special Issue of the Journal of Parallel Algorithms and Applications on Optimising Compilers for Parallel Languages. Parallel Algorithms Appl. 7(3-4): 313 (1995) - [j6]Boleslaw K. Szymanski
, William Maniatty, Balaram Sinharoy:
Simultaneous Parallel Reduction on SIMD Machines. Parallel Process. Lett. 5: 437-449 (1995) - 1994
- [j5]Balaram Sinharoy, Boleslaw K. Szymanski:
Data and Task Alignment in Distributed Memory Architectures. J. Parallel Distributed Comput. 21(1): 61-74 (1994) - [j4]Balaram Sinharoy, Boleslaw K. Szymanski:
Finding Optimum Wavefront of Parallel Computation. Parallel Algorithms Appl. 2(1-2): 5-26 (1994) - [j3]Can C. Özturan, Balaram Sinharoy, Boleslaw K. Szymanski:
Compiler Technology for Parallel Scientific Computation. Sci. Program. 3(3): 201-225 (1994) - 1992
- [j2]Boleslaw K. Szymanski, Balaram Sinharoy:
Complexity of the Closest Vector Problem in a Lattice Generated by (0, 1)-Matrix. Inf. Process. Lett. 42(3): 121-126 (1992) - [j1]Boleslaw K. Szymanski, Balaram Sinharoy:
Corrigenda: Complexity of the Closest Vector Problem in a Lattice Generated by (0, 1)-Matrix. Inf. Process. Lett. 43(3): 167 (1992)
Conference and Workshop Papers
- 2021
- [c11]Brian W. Thompto, Dung Q. Nguyen, José E. Moreira, Ramon Bertran, Hans M. Jacobson, Richard J. Eickemeyer, Rahul M. Rao, Michael Goulet, Marcy Byers, Christopher J. Gonzalez, Karthik Swaminathan, Nagu R. Dhanwada, Silvia M. Müller, Andreas Wagner, Satish Kumar Sadasivam, Robert K. Montoye, William J. Starke, Christian G. Zoellin, Michael S. Floyd, Jeffrey Stuecheli, Nandhini Chandramoorthy, John-David Wellman, Alper Buyuktosunoglu, Matthias Pflanz, Balaram Sinharoy, Pradip Bose:
Energy Efficiency Boost in the AI-Infused POWER10 Processor. ISCA 2021: 29-42 - 2014
- [c10]Joshua Friedrich, Hung Q. Le, William J. Starke, Jeff Stuecheli, Balaram Sinharoy, Eric J. Fluhr, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, David Hogenmiller, Frank Malgioglio, Ryan Nett, Ruchir Puri, Phillip J. Restle, David Shan, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler, Dave W. Victor:
The POWER8TM processor: Designed for big data, analytics, and cloud environments. ICICDT 2014: 1-4 - 2010
- [c9]Dieter F. Wendel, Ronald N. Kalla, Robert Cargnoni, Joachim G. Clabes, Joshua Friedrich, Roland Frech, James A. Kahle, Balaram Sinharoy, William J. Starke, Scott A. Taylor, Steve Weitzel, Sam G. Chu, Md. Saiful Islam, Victor V. Zyuban:
The implementation of POWER7TM: A highly parallel and scalable multi-core high-end server processor. ISSCC 2010: 102-103 - 2009
- [c8]Ronald N. Kalla, Balaram Sinharoy:
POWER7: IBM's next generation server processor. Hot Chips Symposium 2009: 1-12 - [c7]Balaram Sinharoy:
POWER7 multi-core processor design. MICRO 2009: 1 - 2005
- [c6]Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Richard J. Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler:
Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors. HPCA 2005: 238-242 - 2004
- [c5]Joachim G. Clabes, Joshua Friedrich, Mark Sweet, Jack DiLullo, Sam G. Chu, Donald W. Plass, James Dawson, Paul Muench, Larry Powell, Michael S. Floyd, Balaram Sinharoy, Mike Lee, Michael Goulet, James Wagoner, Nicole S. Schwartz, Stephen L. Runyon, Gary Gorman, Phillip J. Restle, Ronald N. Kalla, Joseph McGill, J. Steve Dodson:
Design and implementation of the POWER5 microprocessor. DAC 2004: 670-672 - 2002
- [c4]Wael El-Essawy, David H. Albonesi, Balaram Sinharoy:
A microarchitectural-level step-power analysis tool. ISLPED 2002: 263-266 - 1996
- [c3]Balaram Sinharoy, Rama Govindaraju:
Improving Software MP Efficiency for Shared Memory Systems. HICSS (1) 1996: 111-120 - 1995
- [c2]Balaram Sinharoy:
Compiling for Multithreaded Multicomputer. LCR 1995: 137-152 - 1992
- [c1]William Maniatty, Boleslaw K. Szymanski, Balaram Sinharoy:
Efficiency of Data Alignment on Maspar. SIGPLAN Workshop 1992: 48-51
Editorship
- 1996
- [e1]Boleslaw K. Szymanski, Balaram Sinharoy:
Languages, Compilers and Run-Time Systems for Scalable Computers, Third Workshop, LCR 1995, Troy, NY, USA, May 1995. Springer 1996, ISBN 978-1-4613-5979-1 [contents]
Coauthor Index
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