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ORCIDThomas J. Bucelot
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Journal Articles
- 2009
[j3]Steven C. Chan, Phillip J. Restle, Thomas J. Bucelot, John S. Liberty, Stephen Weitzel, John M. Keaty, Brian K. Flachs, Richard Volant, Peter Kapusta, Jeffrey S. Zimmerman:
A Resonant Global Clock Distribution for the Cell Broadband Engine Processor. IEEE J. Solid State Circuits 44(1): 64-72 (2009)- 2003
- [j2]Xuejue Huang, Phillip J. Restle, Thomas J. Bucelot, Yu Cao, Tsu-Jae King, Chenming Hu:
Loop-based interconnect modeling and optimization approach for multigigahertz clock network design. IEEE J. Solid State Circuits 38(3): 457-463 (2003) - 2002
- [j1]Gregory P. Rodgers, Isidore G. Bendrihem, Thomas J. Bucelot, Barry D. Burchett, John C. Collins:
Infrastructure requirements for a large-scale, multi-site VLSI development project. IBM J. Res. Dev. 46(1): 87-96 (2002)
Conference and Workshop Papers
- 2015
- [c6]David Shan, Phillip J. Restle, Doug Malone, Robert A. Groves, Eric Lai, Michael Koch, Jason Hibbeler, Yong Kim, Christos Vezyrtzis, Jan Feder, David Hogenmiller, Thomas J. Bucelot:
Resonant clock mega-mesh for the IBM z13TM. VLSIC 2015: 322- - 2014
- [c5]Phillip J. Restle, David Shan, David Hogenmiller, Yong Kim, Alan J. Drake, Jason Hibbeler, Thomas J. Bucelot, Gregory S. Still, Keith A. Jenkins, Joshua Friedrich:
5.3 Wide-frequency-range resonant clock with on-the-fly mode changing for the POWER8TM microprocessor. ISSCC 2014: 100-101 - 2013
- [c4]Keith A. Jenkins, Phillip J. Restle, P. Z. Wang, D. Hogenmiller, David W. Boerstler, Thomas J. Bucelot:
On-chip circuit for measuring multi-GHz clock signal waveforms. VTS 2013: 1-4 - 2008
- [c3]Steven C. Chan, Phillip J. Restle, Thomas J. Bucelot, Steve Weitzel, John M. Keaty, John S. Liberty, Brian K. Flachs, Richard Volant, Peter Kapusta, Jeffrey S. Zimmerman:
A Resonant Global Clock Distribution for the Cell Broadband-Engine Processor. ISSCC 2008: 512-513 - 2005
- [c2]Gerald G. Lopez
, Giovanni Fiorenza, Thomas J. Bucelot, Phillip J. Restle, Mary Yvonne Lanzerotti:
Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution. ACM Great Lakes Symposium on VLSI 2005: 38-43 - 2002
- [c1]Xuejue Huang, Phillip J. Restle, Thomas J. Bucelot, Yu Cao, Tsu-Jae King:
Loop-based interconnect modeling and optimization approach for multi-GHz clock network design. CICC 2002: 19-22
Coauthor Index
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