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Journal Articles
- 2021
[j2]V. Malsoru, A. R. Naseer, G. Narsimha:
Two-way distributed sequential pattern mining using fruit fly algorithm along with Hadoop and map reduce framework. Int. J. Comput. Aided Eng. Technol. 14(4): 503-519 (2021)- 1998
- [j1]A. R. Naseer, M. Balakrishnan, Anshul Kumar:
Direct mapping of RTL structures onto LUT-based FPGA's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(7): 624-631 (1998)
Conference and Workshop Papers
- 2007
- [c7]Ismat K. Maarouf, A. R. Naseer:
WSNodeRater - An Optimized Reputation System Framework for Security Aware Energy Efficient Geographic Routing in WSNs. AICCSA 2007: 258-265 - 2006
- [c6]Ismat K. Maarouf, A. R. Naseer:
SNARE: sensor node attached reputation evaluator. CoNEXT 2006: 29 - 1997
- [c5]A. R. Naseer, M. Balakrishnan, Anshul Kumar:
Optimal Clock Period for Synthesized Data Paths. VLSI Design 1997: 134-139 - 1995
- [c4]A. R. Naseer, M. Balakrishnan, Anshul Kumar:
Delay Minimal Mapping of RTL Structures onto LUT Based FPGAs. FPL 1995: 139-148 - 1994
- [c3]A. R. Naseer, M. Balakrishnan, Anshul Kumar:
An Efficient Technique for Mapping RTL Structures onto FPGAs. FPL 1994: 99-110 - [c2]A. R. Naseer, M. Balakrishnan, Anshul Kumar:
FAST: FPGA Targeted RTL Structure Synthesis Technique. VLSI Design 1994: 21-24 - 1993
- [c1]C. S. Ajay, M. Balakrishnan, D. Harikrishna, M. Karunakaran, Anshul Kumar, Shashi Kumar, V. Mudgil, A. R. Naseer:
High Level Design Experiences with IDEAS. VLSI Design 1993: 110
Coauthor Index
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