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ORCIDMike Schlansker
Person information
- affiliation: Hewlett Packard Enterprise Labs, Palo Alto, CA, USA
- affiliation: Hewlett-Packard Labs
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Journal Articles
- 2016
[j13]Onur Mutlu, Rich Belgard, Nick Tredennick, Mike Schlansker:
The 2014 MICRO Test of Time Award Winners: From 1978 to 1992. IEEE Micro 36(1): 60- (2016)- 2005
- [j12]Jack Sampson, Rubén González, Jean-Francois Collard, Norman P. Jouppi, Michael S. Schlansker:
Fast synchronization for chip multiprocessors. SIGARCH Comput. Archit. News 33(4): 64-69 (2005) - 2001
- [j11]B. Ramakrishna Rau, Michael S. Schlansker:
Embedded Computer Architecture and Automation. Computer 34(4): 75-83 (2001) - [j10]Michael S. Schlansker, Chris J. Newburn:
Guest Editors' Introduction. J. Instr. Level Parallelism 3 (2001) - [j9]Vinod Kathail, Michael S. Schlansker, B. Ramakrishna Rau:
Compiling for EPIC architectures. Proc. IEEE 89(11): 1676-1693 (2001) - [j8]Scott A. Mahlke, Rajiv A. Ravindran, Michael S. Schlansker, Robert Schreiber, Timothy Sherwood
:
Bitwidth cognizant architecture synthesis of custom hardwareaccelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(11): 1355-1371 (2001) - 2000
- [j7]Michael S. Schlansker, B. Ramakrishna Rau:
EPIC: Explicititly Parallel Instruction Computing. Computer 33(2): 37-45 (2000) - 1997
- [j6]Thomas M. Conte, Pradeep K. Dubey, Matthew D. Jennings, Ruby B. Lee, Alex Peleg, Salliah Rathnam, Michael S. Schlansker, Peter Song, Andrew Wolfe:
Challenges to Combining General-Purpose and Multimedia Processors. Computer 30(12): 33-37 (1997) - [j5]Michael S. Schlansker, Thomas M. Conte, James C. Dehnert, Kemal Ebcioglu, Jesse Zhixi Fang, Carol L. Thompson:
Compilers for Instruction-Level Parallelism. Computer 30(12): 63-69 (1997) - [j4]Michael S. Schlansker, Vinod Kathail:
Techniques for critical path reduction of scalar programs. Int. J. Parallel Program. 25(3): 147-181 (1997) - 1996
- [j3]Michael S. Schlansker, Vinod Kathail, Sadun Anik:
Parallelization of Control Recurrences for ILP Processors. Int. J. Parallel Program. 24(1): 65-102 (1996) - 1993
- [j2]Scott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker:
Sentinel Scheduling for VLIW and Superscalar Processors. ACM Trans. Comput. Syst. 11(4): 376-408 (1993) - 1991
- [j1]Parthasarathy P. Tirumalai, Meng Lee, Michael S. Schlansker:
Parallelization of WHILE loops on pipelined architectures. J. Supercomput. 5(2-3): 119-136 (1991)
Conference and Workshop Papers
- 2017
- [c29]Guyue Liu, K. K. Ramakrishnan, Mike Schlansker, Jean Tourrilhes, Timothy Wood:
Design Challenges for High Performance, Scalable NFV Interconnects. KBNets@SIGCOMM 2017: 49-54 - 2015
- [c28]Yiting Xia, Mike Schlansker, T. S. Eugene Ng, Jean Tourrilhes:
Enabling Topological Flexibility for Data Centers Using OmniSwitch. HotCloud 2015 - 2013
- [c27]Michael S. Schlansker, Michael R. T. Tan, Jean Tourrilhes, Jose Renato Santos, Shih-Yuan Wang:
Configurable optical interconnects for scalable datacenters. OFC/NFOEC 2013: 1-3 - 2012
- [c26]Hyojoon Kim, Mike Schlansker, Jose Renato Santos, Jean Tourrilhes, Yoshio Turner, Nick Feamster:
CORONET: Fault tolerance for Software Defined Networks. ICNP 2012: 1-2 - 2011
- [c25]Wenfei Wu, Yoshio Turner, Mike Schlansker:
Routing Optimization for Ensemble Routing. ANCS 2011: 97-98 - 2010
- [c24]Mike Schlansker, Yoshio Turner, Jean Tourrilhes, Alan Karp:
Ensemble routing for datacenter networks. ANCS 2010: 23 - [c23]Mike Schlansker, Jean Tourrilhes, Yoshio Turner, Jose Renato Santos:
Killer Fabrics for Scalable Datacenters. ICC 2010: 1-6 - 2009
- [c22]Mike Schlansker, Jean Tourrilhes, Yoshio Turner, Jose Renato Santos:
Hash-based routing for scalable datacenters. ANCS 2009: 80-81 - 2007
- [c21]Michael S. Schlansker, Nagabhushan Chitlur, Erwin Oertli, Paul M. Stillwell Jr., Linda Rankin, Dennis Bradford, Richard J. Carter, Jayaram Mudigonda, Nathan L. Binkert, Norman P. Jouppi:
High-performance ethernet-based communications for future multi-core processors. SC 2007: 37 - 2006
- [c20]Jack Sampson, Rubén González, Jean-Francois Collard, Norman P. Jouppi, Michael S. Schlansker, Brad Calder:
Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers. MICRO 2006: 235-246 - 2005
- [c19]Hongtao Zhong, Kevin Fan, Scott A. Mahlke, Michael S. Schlansker:
A Distributed Control Path Architecture for VLIW Processors. IEEE PACT 2005: 197-206 - 2003
- [c18]Michael S. Schlansker:
In Memory of Bob Rau. MICRO 2003: 165-168 - 2001
- [c17]Shail Aditya, Michael S. Schlansker:
ShiftQ: a bufferred interconnect for custom loop accelerators. CASES 2001: 158-167 - 2000
- [c16]B. Ramakrishna Rau, Michael S. Schlansker:
Embedded Computing: New Directions in Architecture and Automation. HiPC 2000: 225-244 - 1999
- [c15]Michael S. Schlansker, Scott A. Mahlke, Richard Johnson:
Control CPR: A Branch Height Reduction Optimization for EPIC Architectures. PLDI 1999: 155-168 - 1996
- [c14]Chandra Chekuri, Richard Johnson, Rajeev Motwani, B. Natarajan, B. Ramakrishna Rau, Michael S. Schlansker:
Profile-driven Instruction Level Parallel Scheduling with Application to Super Blocks. MICRO 1996: 58-67 - [c13]Richard Johnson, Michael S. Schlansker:
Analysis Techniques for Predicated Code. MICRO 1996: 100-113 - [c12]David M. Gillies, Roy Dz-Ching Ju, Richard Johnson, Michael S. Schlansker:
Global Predicate Analysis and Its Application to Register Allocation. MICRO 1996: 114-125 - 1995
- [c11]Michael S. Schlansker, Vinod Kathail:
Critical path reduction for scalar programs. MICRO 1995: 57-69 - [c10]B. Natarajan, Michael S. Schlansker:
Spill-free parallel scheduling of basic blocks. MICRO 1995: 119-124 - 1994
- [c9]Michael S. Schlansker, Vinod Kathail, Sadun Anik:
Height reduction of control recurrences for ILP processors. MICRO 1994: 40-51 - 1993
- [c8]Michael S. Schlansker, Vinod Kathail:
Acceleration of First and Higher Order Recurrences on Processors with Instruction Level Parallelism. LCPC 1993: 406-429 - 1992
- [c7]Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker:
Sentinel Scheduling for VLIW and Superscalar Processors. ASPLOS 1992: 238-247 - [c6]B. Ramakrishna Rau, Michael S. Schlansker, Parthasarathy P. Tirumalai:
Code generation schema for modulo scheduled loops. MICRO 1992: 158-169 - [c5]B. Ramakrishna Rau, Meng Lee, Parthasarathy P. Tirumalai, Michael S. Schlansker:
Register Allocation for Software Pipelined Loops. PLDI 1992: 283-299 - 1990
- [c4]Parthasarathy P. Tirumalai, Meng Lee, Michael S. Schlansker:
Parallelization of loops with exits on pipelined architectures. SC 1990: 200-212 - 1989
- [c3]B. Ramakrishna Rau, Michael S. Schlansker, David W. L. Yen:
The Cydram 5 Stride-Insensitive Memory System. ICPP (1) 1989: 242-246 - 1982
- [c2]Pradip Bose, B. Ramakrishna Rau, Michael S. Schlansker:
Systematically derived instruction sets for high-level language support. ACM Southeast Regional Conference 1982: 73-84 - 1973
- [c1]David J. DeWitt, Michael S. Schlansker, Daniel E. Atkins:
A microprogramming language for the B-1726. MICRO 1973: 21-29
Editorship
- 2000
- [e1]Andrew Wolfe, Michael S. Schlansker:
Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 33, Monterey, California, USA, December 10-13, 2000. ACM/IEEE Computer Society 2000, ISBN 0-7695-0924-x [contents]
Reference Works
- 2011
- [r1]Michael S. Schlansker:
Cydra 5. Encyclopedia of Parallel Computing 2011: 488-497
Coauthor Index
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