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ORCIDMohammed Zackriya V
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Journal Articles
- 2020
[j6]Mehmet Meric Isgenc
, Mayler G. A. Martins, V. Mohammed Zackriya, Samuel N. Pagliarini, Lawrence T. Pileggi:
Logic IP for Low-Cost IC Design in Advanced CMOS Nodes. IEEE Trans. Very Large Scale Integr. Syst. 28(2): 585-595 (2020)- 2017
- [j5]Mohammed Zackriya V, Harish M. Kittur:
Content Addressable Memory - Early Predict and Terminate Precharge of Match-Line. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 385-387 (2017) - 2016
- [j4]V. Mohammed Zackriya, Harish M. Kittur:
Low Energy Metric Content Addressable Memory (CAM) with Multi Voltage Matchline Segments. J. Circuits Syst. Comput. 25(2): 1650002:1-1650002:10 (2016) - [j3]V. Mohammed Zackriya, Harish M. Kittur:
Precharge-Free, Low-Power Content-Addressable Memory. IEEE Trans. Very Large Scale Integr. Syst. 24(8): 2614-2621 (2016) - 2014
- [j2]V. Mohammed Zackriya, John Reuben, Ashim Harsh, Harish M. Kittur:
Low Power fractional-n frequency Divider with Improved Resolution. J. Circuits Syst. Comput. 23(8) (2014) - 2013
- [j1]John Reuben, V. Mohammed Zackriya, Salma Nashit, Harish M. Kittur:
Capacitance driven clock mesh synthesis to minimize skew and power dissipation. IEICE Electron. Express 10(24): 20130850 (2013)
Conference and Workshop Papers
- 2021
- [c2]Prashanth Mohan, Oguz Atli, Onur O. Kibar, V. Mohammed Zackriya, Larry T. Pileggi, Ken Mai:
Top-down Physical Design of Soft Embedded FPGA Fabrics. FPGA 2021: 1-10 - 2020
- [c1]Joseph Sweeney, V. Mohammed Zackriya, Samuel Pagliarini, Lawrence T. Pileggi:
Latch-Based Logic Locking. HOST 2020: 132-141
Informal and Other Publications
- 2020
- [i2]Joseph Sweeney, Mohammed Zackriya V, Samuel Pagliarini, Lawrence T. Pileggi:
Latch-Based Logic Locking. CoRR abs/2005.10649 (2020) - 2014
- [i1]V. Mohammed Zackriya, Harish M. Kittur:
Selective Match-Line Energizer Content Addressable Memory(SMLE -CAM). CoRR abs/1406.7662 (2014)
Coauthor Index
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