Jiun-In Guo

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Chih-Da Chien

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Publications

2009
[j15]
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Chih-Da Chien, Cheng-An Chien, Jui-Chin Chu, Jiun-In Guo, Ching-Hwa Cheng:
A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications. ACM Trans. Design Autom. Electr. Syst. 14(1): 17:1-17:17 (2009)
[c53]
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Cheng-An Chien, Chih-Da Chien, Jui-Chin Chu, Jiun-In Guo, Ching-Hwa Cheng:
A Multi-standard Video Decoder for High Definition Video Applications. ISCAS 2009: 1933
2007
[c42]
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  - conf/icmcs/ChienWLHCG07
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Chih-Da Chien, Chih-Wei Wang, Chiun-Chau Lin, Tien-Wei Hsieh, Yuan-Hwa Chu, Jiun-In Guo:
A Low Latency Memory Controller for Video Coding Systems. ICME 2007: 1211-1214
[c41]
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Guo-An Jian, Chih-Da Chien, Jiun-In Guo:
A Memory-Based Hardware Accelerator for Real-Time MPEG-4 Audio Coding and Reverberation. ISCAS 2007: 1569-1572
[c38]
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  - conf/isscc/ChienLSCHYCCG07
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Chih-Da Chien, Chien-Chang Lin, Yi-Hung Shih, He-Chun Chen, Chia-Jui Huang, Cheng-Yen Yu, Chih-Liang Chen, Ching-Hwa Cheng, Jiun-In Guo:
A 252kgate/71mW Multi-Standard Multi-Channel Video Decoder for High Definition Video Applications. ISSCC 2007: 282-603
2006
[j12]
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  - journals/tcsv/ChienLCGCS06
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Chih-Da Chien, Keng-Po Lu, Yu-Min Chen, Jiun-In Guo, Yuan-Sun Chu, Ching-Lung Su:
An Area-Efficient Variable Length Decoder IP Core Design for MPEG-1/2/4 Video Coding Applications. IEEE Trans. Circuits Syst. Video Technol. 16(9): 1172-1178 (2006)
[c27]
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Chih-Da Chien, Keng-Po Lu, Yi-Hung Shih, Jiun-In Guo:
A high performance CAVLC encoder design for MPEG-4 AVC/H.264 video coding applications. ISCAS 2006
2005
[c24]
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  - conf/iscas/ChienCHG05
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Chih-Da Chien, Ho-Chun Chen, Lin-Chieh Huang, Jiun-In Guo:
A low-power motion compensation IP core design for MPEG-1/2/4 video decoding. ISCAS (5) 2005: 4542-4545
2004
[c21]
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  - conf/icmcs/ChangTCLG04
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Tai-Lun Chang, Ying-Ming Tsai, Chih-Da Chien, Chien-Chang Lin, Jiun-In Guo:
A high-performance MPEG4 bitstream processing core. ICME 2004: 467-470
[c18]
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Chih-Da Chien, Chien-Chang Lin, Jiun-In Guo, Tien-Fu Chen:
A power-aware IP core generator for the one-dimensional discrete Fourier transform. ISCAS (3) 2004: 637-640
2003
[c15]
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  - conf/iscas/GuoCL03
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Jiun-In Guo, Chih-Da Chien, Chien-Chang Lin:
A parameterized low power design for the variable-length discrete Fourier transform using dynamic pipelining. ISCAS (5) 2003: 293-296
2002
[j5]
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  - journals/jcsc/GuoLC02
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Jiun-In Guo, Chien-Chang Lin, Chih-Da Chien:
A Low-Power Parameterized Hardware Design for the One-Dimensional Discrete Fourier Transform of Variable Lengths. J. Circuits Syst. Comput. 11(4): 405-428 (2002)

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