default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDHabib Mehrez
- > Home > Persons > Habib Mehrez
Publications
- 2017
[j24]Sonda Chtourou, Zied Marrakchi, Emna Amouri, Vinod Pangracious
, Mohamed Abid, Habib Mehrez:
Performance analysis and optimization of cluster-based mesh FPGA architectures: design methodology and CAD tool support. Turkish J. Electr. Eng. Comput. Sci. 25: 2044-2054 (2017)- [c90]Sonda Chtourou, Mohamed Abid, Zied Marrakchi, Emna Amouri, Habib Mehrez:
On Exploiting Partitioning-Based Placement Approach for Performances Improvement of 3D FPGA. HPCS 2017: 572-579 - 2016
- [j22]Sonda Chtourou, Zied Marrakchi, Emna Amouri, Vinod Pangracious, Mohamed Abid, Habib Mehrez:
Improvement of cluster-based Mesh FPGA architecture using novel hierarchical interconnect topology and long routing wires. Microprocess. Microsystems 40: 16-26 (2016) - [c86]Sonda Chtourou, Mohamed Abid, Zied Marrakchi, Emna Amouri, Habib Mehrez:
Design of advanced 2D and 3D FPGAs: Architecture-level exploration and algorithm-level optimization. IDT 2016: 31-36 - [c84]Sonda Chtourou, Mohamed Abid, Zied Marrakchi, Emna Amouri, Habib Mehrez:
The effect of interconnect depopulation on FPGA performances in terms of power, area and delay. HPCS 2016: 104-111 - [c83]Sonda Chtourou, Zied Marrakchi, Emna Amouri, Vinod Pangracious, Habib Mehrez, Mohamed Abid:
Exploration of Mesh-Based FPGA Architecture: Comparison of 2D and 3D Technologies in Terms of Power, Area and Performance. PDP 2016: 635-642 - 2015
- [b1]Vinod Pangracious, Zied Marrakchi, Habib Mehrez:
Three-Dimensional Design Methodologies for Tree-based FPGA Architecture. Lecture Notes in Electrical Engineering 350, Springer 2015, ISBN 978-3-319-19173-7, pp. 1-209 - [j21]Mariem Turki, Zied Marrakchi, Habib Mehrez, Mohamed Abid:
Signal multiplexing approach to improve inter-FPGA bandwidth of prototyping platform. Des. Autom. Embed. Syst. 19(3): 223-242 (2015) - [j20]Nidhameddine Belhadj, Nejmeddine Bahri, Zied Marrakchi, Mohamed Ali Ben Ayed, Nouri Masmoudi, Habib Mehrez:
H.264/AVC high definition intra coding implementation on multiprocessor system on chip technology architecture. IET Comput. Digit. Tech. 9(5): 259-267 (2015) - [j19]Vinod Pangracious, Zied Marrakchi, Habib Mehrez:
Design and Optimization of a Horizontally Partitioned, High-Speed, 3D Tree-Based FPGA. IEEE Micro 35(6): 48-59 (2015) - [c81]Sonda Chtourou, Zied Marrakchi, Vinod Pangracious, Emna Amouri, Habib Mehrez, Mohamed Abid:
Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization. ARC 2015: 411-418 - 2014
- [j18]Nidhameddine Belhadj, Zied Marrakchi, Mohamed Ali Ben Ayed, Nouri Masmoudi, Habib Mehrez:
MPSoC Architecture for Macro Blocks Line Partitioning of H.264/AVC Encoder. Int. J. Embed. Real Time Commun. Syst. 5(2): 43-60 (2014) - [j16]Alp Kiliç, Zied Marrakchi, Habib Mehrez:
A Top-Down Optimization Methodology for Mutually Exclusive Applications. Int. J. Reconfigurable Comput. 2014: 827613:1-827613:18 (2014) - [j14]Vinod Pangracious, Emna Amouri, Zied Marrakchi, Habib Mehrez:
Architecture level optimization of 3-dimensional tree-based FPGA. Microelectron. J. 45(4): 355-366 (2014) - [c80]Sonda Chtourou, Mohamed Abid, Vinod Pangracious, Emna Amouri, Zied Marrakchi, Habib Mehrez:
Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation. 3DIC 2014: 1-7 - [c78]Nidhameddine Belhadj, Mohamed Ali Ben Ayed, Nouri Masmoudi, Zied Marrakchi, Habib Mehrez:
MPSoC architecture for Component Level Parallelism of H.264/AVC intra prediction encoding chain on SoCLib platform. ATSIP 2014: 153-157 - [c77]Sonda Chtourou, Mohamed Abid, Zied Marrakchi, Habib Mehrez:
Power consumption analysis for mesh based FPGA. DTIS 2014: 1-5 - [c76]Vinod Pangracious, Zied Marrakchi, Nizar Beltaief, Habib Mehrez, Umer Farooq:
Exploration and optimization of heterogeneous interconnect fabric of 3D tree-based FPGA. DTIS 2014: 1-6 - [c74]Karim M. Abdellatif, Roselyne Chotin-Avot, Zied Marrakchi, Habib Mehrez, Qingshan Tang:
Towards high performance GHASH for pipelined AES-GCM using FPGAs (abstract only). FPGA 2014: 242 - [c69]Saif-Ur Rehman, Adrien Blanchardon, Arwa Ben Dhia, Mounir Benabdenbi, Roselyne Chotin-Avot, Lirida A. B. Naviner, Lorena Anghel, Habib Mehrez, Emna Amouri, Zied Marrakchi:
Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA. ISVLSI 2014: 553-558 - [c65]Vinod Pangracious, Mohamed Sahbi Marrakchi, Habib Mehrez, Zied Marrakchi:
On wiring delays reduction of tree-based FPGA using 3-D fabric. SoCC 2014: 64-69 - [c64]Abdulfattah Mohammad Obeid, Syed Manzoor Qasim, Mohammed S. BenSaleh, Zied Marrakchi, Habib Mehrez, Heni Ghariani, Mohamed Abid:
Flexible reconfigurable architecture for DSP applications. SoCC 2014: 204-209 - 2013
- [j12]Emna Amouri, Habib Mehrez, Zied Marrakchi:
Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA. Int. J. Reconfigurable Comput. 2013: 802436:1-802436:24 (2013) - [j11]Mariem Turki, Zied Marrakchi, Habib Mehrez, Mohamed Abid:
Frequency Optimization Objective during System Prototyping on Multi-FPGA Platform. Int. J. Reconfigurable Comput. 2013: 853510:1-853510:12 (2013) - [j9]Umer Farooq, Husain Parvez, Habib Mehrez, Zied Marrakchi:
Exploration and optimization of a homogeneous tree-based application specific inflexible FPGA. Microelectron. J. 44(12): 1052-1062 (2013) - [c63]Vinod Pangracious, Habib Mehrez, Zied Marrakchi:
Designing a 3D tree-based FPGA: Optimization of butterfly programmable interconnect topology using 3D technology. 3DIC 2013: 1-8 - [c62]Nidhameddine Belhadj, Nejmeddine Bahri, Mohamed Ali Ben Ayed, Zied Marrakchi, Habib Mehrez:
Data level parallelism for H264/AVC baseline intra-prediction chain on MPSoC. SSD 2013: 1-4 - [c61]Vinod Pangracious, Zied Marrakchi, Emna Amouri, Habib Mehrez:
Performance Analysis and Optimization of High Density Tree-Based 3D Multilevel FPGA. ARC 2013: 197-209 - [c60]Mariem Turki, Zied Marrakchi, Habib Mehrez, Mohamed Abid:
Iterative Routing Algorithm of Inter-FPGA Signals for Multi-FPGA Prototyping Platform. ARC 2013: 210-217 - [c59]Qingshan Tang, Matthieu Tuna, Zied Marrakchi, Habib Mehrez:
Automatic Design Flow for Creating a Custom Multi-FPGA Board Netlist. ARC 2013: 221 - [c58]Vinod Pangracious, Habib Mehrez, Zied Marrakchi:
Architecture level TSV count minimization methodology for 3D tree-based FPGA. COOL Chips 2013: 1-3 - [c57]Vinod Pangracious, Habib Mehrez, Umer Farooq, Zied Marrakchi:
High performance 3-dimensional heterogeneous tree-based FPGA architectures (HT-FPGA). FPGAworld 2013: 3:1-3:6 - [c56]Vinod Pangracious, Zied Marrakchi, Habib Mehrez:
Design and optimization of heterogeneous tree-based FPGA using 3D technology. FPT 2013: 334-337 - [c55]Arwa Ben Dhia, Saif-Ur Rehman, Adrien Blanchardon, Lirida A. B. Naviner, Mounir Benabdenbi, Roselyne Chotin-Avot, Emna Amouri, Habib Mehrez, Zied Marrakchi:
A defect-tolerant cluster in a mesh SRAM-based FPGA. FPT 2013: 434-437 - [c54]Vinod Pangracious, Emna Amouri, Habib Mehrez, Zied Marrakchi:
Physical design exploration of 3D tree-based FPGA architecture. ACM Great Lakes Symposium on VLSI 2013: 335-336 - [c53]Vinod Pangracious, Habib Mehrez, Zied Marrakchi:
TSV count minimization and thermal analysis for 3D Tree-based FPGA. ICICDT 2013: 223-226 - [c52]Mariem Turki, Habib Mehrez, Zied Marrakchi, Mohamed Abid:
Partitioning constraints and signal routing approach for multi-FPGA prototyping platform. ISSoC 2013: 1-4 - [c48]Vinod Pangracious, Habib Mehrez, Zied Marrakchi:
Designing 3D tree-based FPGA: Interconnect optimization and thermal analysis. NEWCAS 2013: 1-4 - [c45]Emna Amouri, Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Zied Marrakchi:
Efficient multilevel interconnect topology for cluster-based mesh FPGA architecture. ReConFig 2013: 1-6 - [c44]Vinod Pangracious, Habib Mehrez, Nizar Beltaief, Zied Marrakchi, Umer Farooq:
Exploration environment for 3D heterogeneous tree-based FPGA architectures (3D HT-FPGA). ReConFig 2013: 1-6 - 2012
- [j7]Umer Farooq, Husain Parvez, Habib Mehrez, Zied Marrakchi:
A new heterogeneous tree-based application specific FPGA and its comparison with mesh-based application specific FPGA. Microprocess. Microsystems 36(8): 588-605 (2012) - [c40]Alp Kiliç, Zied Marrakchi, Matthieu Tuna, Habib Mehrez:
A logic sharing synthesis tool for mutually exclusive applications. DTIS 2012: 1-6 - [c38]Mariem Turki, Habib Mehrez, Zied Marrakchi:
Multi-FPGA prototyping environment: Large benchmark generation and signals routing. ReConFig 2012: 1-6 - 2011
- [j6]Umer Farooq, Husain Parvez, Habib Mehrez, Zied Marrakchi:
Exploration of Heterogeneous FPGA Architectures. Int. J. Reconfigurable Comput. 2011: 121404:1-121404:18 (2011) - [j5]Husain Parvez, Zied Marrakchi, Alp Kiliç, Habib Mehrez:
Application-Specific FPGA using heterogeneous logic blocks. ACM Trans. Reconfigurable Technol. Syst. 4(3): 24:1-24:14 (2011) - [c36]Umer Farooq, Husain Parvez, Zied Marrakchi, Habib Mehrez:
Comparison between Heterogeneous Mesh-Based and Tree-Based Application Specific FPGA. ARC 2011: 218-229 - [c34]Emna Amouri, Zied Marrakchi, Habib Mehrez:
Differential pair routing to balance dual signals of WDDL designs in cluster-based Mesh FPGA. ReCoSoC 2011: 1-4 - 2010
- [c33]Emna Amouri, Zied Marrakchi, Habib Mehrez:
Controlled placement and routing techniques to improve timing balance of WDDL designs in Mesh-based FPGA. APCCAS 2010: 296-299 - [c32]Zied Marrakchi, Husain Parvez, Alp Kiliç, Habib Mehrez, Hmaied Marrakchi:
On the optimization of FPGA area depending on target applications. APCCAS 2010: 308-311 - [c31]Husain Parvez, Zied Marrakchi, Habib Mehrez:
Application Specific FPGA Using Heterogeneous Logic Blocks. ARC 2010: 92-109 - [c30]Husain Parvez, Zied Marrakchi, Habib Mehrez:
Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only). FPGA 2010: 290 - [c28]Mariem Turki, Mohamed Abid, Zied Marrakchi, Habib Mehrez:
Routability driven placement for mesh-based FPGA architecture. IDT 2010: 85-90 - [c27]Umer Farooq, Husain Parvez, Zied Marrakchi, Habib Mehrez:
Exploration of Heterogeneous FPGA Architectures. ReCoSoC 2010: 37-44 - 2009
- [j4]Zied Marrakchi, Hayder Mrabet, Umer Farooq, Habib Mehrez:
FPGA Interconnect Topologies Exploration. Int. J. Reconfigurable Comput. 2009: 259837:1-259837:13 (2009) - [c26]Husain Parvez, Zied Marrakchi, Habib Mehrez:
ASIF: Application Specific Inflexible FPGA. FPT 2009: 112-119 - [c25]Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez:
Placement and routing techniques to improve delay balance of WDDL netlist in MFPGA. ICECS 2009: 791-794 - [c24]Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez:
Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing. ReConFig 2009: 201-206 - 2008
- [c23]Husain Parvez, Zied Marrakchi, Umer Farooq, Habib Mehrez:
A new coarse-grained FPGA architecture exploration environment. FPT 2008: 285-288 - [c22]Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib Mehrez:
Efficient tree topology for FPGA interconnect network. ACM Great Lakes Symposium on VLSI 2008: 321-326 - [c20]Umer Farooq, Zied Marrakchi, Hayder Mrabet, Habib Mehrez:
The Effect of LUT and Cluster Size on a Tree Based FPGA Architecture. ReConFig 2008: 115-120 - [c19]Husain Parvez, Zied Marrakchi, Habib Mehrez:
Enhanced Methodology and Tools for Exploring Domain-Specific Coarse-Grained FPGAs. ReConFig 2008: 121-126 - 2007
- [c18]Zied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez:
Efficient Mesh of Tree Interconnect for FPGA Architecture. FPT 2007: 269-272 - [c17]Zied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez:
Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances. NOCS 2007: 243-252 - 2006
- [c16]Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez:
A multilevel hierarchical interconnection structure for FPGA. FPGA 2006: 225 - [c15]Zied Marrakchi, Hayder Mrabet, Habib Mehrez:
Configuration tools for a new multilevel hierarchical FPGA. FPGA 2006: 229 - [c14]Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez:
Performances improvement of FPGA using novel multilevel hierarchical interconnection structure. ICCAD 2006: 675-679 - [c13]Zied Marrakchi, Hayder Mrabet, Habib Mehrez:
A new Multilevel Hierarchical MFPGA and its suitable configuration tools. ISVLSI 2006: 263-268 - [c12]Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez, André Tissot:
Performance Improvement of FPGA Using Novel Multilevel Hierarchical Interconnection Structure. ReCoSoC 2006: 117-123 - 2005
- [c11]Zied Marrakchi, Hayder Mrabet, Habib Mehrez:
Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation. ReConFig 2005 - [c10]Hayder Mrabet, Zied Marrakchi, Habib Mehrez, André Tissot:
Implementation of Scalable Embedded FPGA for SOC. ReCoSoC 2005: 59-62
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-04-24 23:16 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
