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ORCIDStanislaw J. Piestrak
- > Home > Persons > Stanislaw J. Piestrak
Publications
- 2015
[c31]B. Chagun Basha, Sébastien Pillement, Stanislaw J. Piestrak:
Fault-aware configurable logic block for reliable reconfigurable FPGAs. ISCAS 2015: 2732-2735- 2014
- [j19]Syed M. A. H. Jafri, Stanislaw J. Piestrak, Ahmed Hemani, Kolin Paul, Juha Plosila
, Hannu Tenhunen:
Private reliability environments for efficient fault-tolerance in CGRAs. Des. Autom. Embed. Syst. 18(3-4): 295-327 (2014) - [j18]Syed M. A. H. Jafri, Stanislaw J. Piestrak, Olivier Sentieys, Sébastien Pillement:
Design of the coarse-grained reconfigurable architecture DART with on-line error detection. Microprocess. Microsystems 38(2): 124-136 (2014) - [c29]B. Chagun Basha, Stanislaw J. Piestrak, Sébastien Pillement:
Built-in 3-Dimensional Hamming Multiple-Error Correcting Scheme to Mitigate Radiation Effects in SRAM-Based FPGAs. ARC 2014: 254-261 - 2013
- [j15]Hung-Manh Pham, Sébastien Pillement, Stanislaw J. Piestrak:
Low-Overhead Fault-Tolerance Technique for a Dynamically Reconfigurable Softcore Processor. IEEE Trans. Computers 62(6): 1179-1192 (2013) - [c27]Syed M. A. H. Jafri, Stanislaw J. Piestrak, Kolin Paul, Ahmed Hemani, Juha Plosila, Hannu Tenhunen:
Energy-Aware Fault-Tolerant CGRAs Addressing Application with Different Reliability Needs. DSD 2013: 525-534 - [c26]Syed M. A. H. Jafri, Stanislaw J. Piestrak, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
Implementation and evaluation of configuration scrubbing on CGRAs: A case study. ISSoC 2013: 1-8 - 2011
- [c24]Muhammad Moazam Azeem, Stanislaw J. Piestrak, Olivier Sentieys, Sébastien Pillement:
Error recovery technique for coarse-grained reconfigurable architectures. DDECS 2011: 441-446 - 2010
- [j14]Stanislaw J. Piestrak, Sébastien Pillement, Olivier Sentieys:
Comments on "A Low-Power Dependable Berger Code for Fully Asymmetric Communication". IEEE Commun. Lett. 14(8): 761-763 (2010) - [j13]Stanislaw J. Piestrak, Sébastien Pillement, Olivier Sentieys:
Designing Efficient Codecs for Bus-Invert Berger Code for Fully Asymmetric Communication. IEEE Trans. Circuits Syst. II Express Briefs 57-II(10): 777-781 (2010) - [c19]Syed M. A. H. Jafri, Stanislaw J. Piestrak, Olivier Sentieys, Sébastien Pillement:
Design of a fault-tolerant coarse-grained. ISQED 2010: 845-852 - 1998
- [c9]Stanislaw J. Piestrak, Fabrice Pedron, Olivier Sentieys:
VLSI implementation and complexity comparison of residue generators modulo 3. EUSIPCO 1998: 1-4
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