default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDMicroprocessors and Microsystems, Volume 28
Volume 28, Number 1, February 2004
- Paula Doyle, Donal Heffernan, D. Duma:
A time-triggered transducer network based on an enhanced IEEE 1451 model. 1-12 - Zoran A. Salcic
, Partha S. Roop, Morteza Biglari-Abhari, Abbas Bigdeli:
REFLIX: a processor core with native support for control-dominated embedded applications. 13-25 - Tomer Karin, Shlomo Weiss:
Programming Windows NT device drivers to operate non-interrupting embedded devices. 27-35 - Kumardeb Banerjee, Bivas Dam, Kalyan Majumdar, R. Banerjee, D. Patranabis:
A carrier peak synchronous direct digital demodulation technique and its FPGA implementation. 37-46
Volume 28, Number 2, March 2004
- Angelo Furfaro, Libero Nigro, Francesco Pupo:
Multimedia synchronization based on aspect oriented programming. 47-56 - Juha Alakarhu, Jarkko Niittylahti:
DRAM performance as a function of its structure and memory stream locality. 57-68 - Antonella Santone, Gigliola Vaglini:
Formula-based abstractions and symbolic execution for model checking programs. 69-76 - Michael S. Grow, Donglok Kim, Yongmin Kim:
Template-based automatic data flow code generation for mediaprocessors. 77-84 - Wensheng Yao, Jinyuan You, Baiyan Li:
Main sequences genetic scheduling for multiprocessor systems using task duplication. 85-94
Volume 28, Number 3, April 2004
- Jung-Hoon Lee, Gi-Ho Park, Shin-Dug Kim:
Dynamic and selective low power data TLB system. 95-105 - Odemir Martinez Bruno, Luciano da Fontoura Costa:
A parallel implementation of exact Euclidean distance transform based on exact dilations. 107-113 - Richard E. Haskell, Darrin M. Hanna:
A VHDL--Forth Core for FPGAs. 115-125 - Marcus Tadeu Pinheiro Silva, Antônio de Pádua Braga, Wilian Soares Lacerda:
Reconfigurable co-processor for Kanerva's sparse distributed memory. 127-134 - Colin Ryan, Donal Heffernan, Gabriel Leen:
Clock synchronisation on multiple TTCAN network channels. 135-146
Volume 28, Number 4, May 2004
- Chao-Chin Wu:
Embedding a superscalar processor onto a chip multiprocessor. 147-156 - Javier P. Gaspar, Suei Feng Chen, Alejandro Gordillo, Mateo Hepp, Pablo A. Ferreyra, Carlos A. Marqués:
Digital lock in amplifier: study, design and development with a digital signal processor. 157-162 - Ola Redell, Jad El-khoury, Martin Törngren:
The AIDA toolset for design and implementation analysis of distributed real-time control systems. 163-182 - Alessandro Cilardo, Antonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese:
Exploring the design-space for FPGA-based implementation of RSA. 183-191
Volume 28, Numbers 5-6, August 2004
- Miguel A. Vega-Rodríguez, Juan Manuel Sánchez-Pérez, Juan Antonio Gómez Pulido:
Guest editors' introduction - Special issue on FPGAs: applications and designs. 193-195 - Valery Sklyarov:
FPGA-based implementation of recursive algorithms. 197-211 - Tom Van Court, Martin C. Herbordt, Richard J. Barton:
Case study of a functional genomics application for an FPGA-based coprocessor. 213-222 - Aristides Nikologiannis, Ioannis Papaefstathiou, George Kornaros, Christopher Kachris:
An FPGA-based queue management system for high speed networking devices. 223-236 - Paul Berube, Mike H. MacGregor, José Nelson Amaral:
FPGA implementation and experimental evaluation of a multizone network cache. 237-252 - Alan Daly, William P. Marnane, Tim Kerins, Emanuel M. Popovici:
An FPGA implementation of a GF(p) ALU for encryption processors. 253-260 - Furi Andi Karnapi, Woon-Seng Gan, Yong Kim Chong:
FPGA implementation of parametric loudspeaker system. 261-272 - Leonardo Maria Reyneri:
A Simulink-based hybrid codesign tool for rapid prototyping of FPGA's in signal processing systems. 273-289 - Javier Resano, Diederik Verkest, Daniel Mozos, Serge Vernalde, Francky Catthoor:
A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs. 291-301 - José Albaladejo, David de Andrés, Lenin Lemus, Joaquim Salvi:
Codesign methodology for computer vision applications. 303-316 - Alireza Ejlali, Seyed Ghassem Miremadi:
FPGA-based fault injection into switch-level models. 317-327 - Francisco Rodríguez-Henríquez, Nazar Abbas Saqib, Arturo Díaz-Pérez:
A fast parallel implementation of elliptic curve point multiplication over GF(2m). 329-339 - Young-Su Kwon, Chong-Min Kyung:
Scheduling driven circuit partitioning algorithm for multiple FPGAs using time-multiplexed, off-chip, multi-casting interconnection architecture. 341-350
Volume 28, Number 7, September 2004
- P. Balasubramanian, P. M. Aravindakshan, K. Parameswaran, V. K. Agrawal:
A simple scheme for PSK demodulation. 351-355 - Gholam-Reza Latif-Shabgahi:
A novel algorithm for weighted average voting used in fault tolerant computing systems. 357-361 - Francisco Fernández, José Ignacio Hidalgo, Juan Lanchares, J. M. Sánchez:
A methodology for reconfigurable hardware design based upon evolutionary computation. 363-371 - Jonas Jalminger, Per Stenström:
A cache block reuse prediction scheme. 373-385 - Omar S. Elkeelany, Ghulam M. Chaudhry:
SPEED: Stand-alone programmable ethernet enabled devices. 387-399
Volume 28, Number 8, October 2004
- Jayasree Dattagupta, Nabanita Das:
Editorial. Microprocess. Microsystems 28(8): 401-402 (2004) - Jagoba Arias, Aitzol Zuloaga, Jesús Lázaro, Jon Andreu, Armando Astarloa:
Malguki: an RSSI based ad hoc location algorithm. 403-409 - Swarup Mandal, Debashis Saha, Ambuj Mahanti:
A real-time heuristic search technique for fixed channel allocation (FCA) in mobile cellular communications. 411-416 - Sajal K. Das, Osman Koyuncu:
Dynamic multi-channel assignment using network flows in wireless data networks. 417-426 - Subhankar Dhar, Michael Q. Rieck, Sukesh Pai, Eun Jik Kim:
Distributed routing schemes for ad hoc networks using d-SPR sets. 427-437 - Vasu Jolly, Naoto Kimura, Shahram Latifi, Pradip K. Srimani:
Loop detection in MPLS for wireless sensor networks. 439-445 - Lalit M. Patnaik, S. Hasan Raza Naqvi:
A review of medium access protocols for mobile ad hoc networks with transmission power control. 447-455 - Yu-Chee Tseng, Ten-Yueng Hsieh:
An architecture for power-saving communications in a wireless mobile ad hoc network based on location information. 457-465 - Wei Ding, S. Sitharama Iyengar, Rajgopal Kannan, William Rummler:
Energy equivalence routing in wireless sensor networks. 467-475
Volume 28, Number 9, November 2004
- Sarp Oral, Alan D. George:
Multicast performance modeling and evaluation for high-speed unidirectional torus networks. 477-489 - Meng Joo Er, Tien Peng Tan, Sin Yee Loh:
Control of a mobile robot using generalized dynamic fuzzy neural networks. 491-498 - Ali M. Elkateeb, Paul C. Richardson, Adnan Shaout, Afzal Hussain, Mohammed Elbeshti:
Scalable ATM network interface design using parallel RISC processors architecture. 499-507 - Ricardo José Colom-Palero, Rafael Gadea Gironés, Francisco José Ballester-Merelo, Marcos Martínez Peiró:
Flexible architecture for the implementation of the two-dimensional discrete wavelet transform (2D-DWT) oriented to FPGA devices. 509-518
Volume 28, Number 10, December 2004
- Aman Garg, A. L. Narasimha Reddy:
Mitigation of DoS attacks through QoS regulation. 521-530 - Yichuan Jiang, Zhengyou Xia, Yiping Zhong, Shiyong Zhang:
Defend mobile agent against malicious hosts in migration itineraries. 531-546 - Yingfei Dong, Changho Choi, Zhi-Li Zhang:
A security framework for protecting traffic between collaborative domains. 547-559 - Ioannis Papaefstathiou, Vassilis Papaefstathiou, Christos P. Sotiriou:
Design-space exploration of the most widely used cryptography algorithms. 561-571 - Darshan Sonecha, Bo Yang, Ramesh Karri, David A. McGrew:
High speed architectures for Leviathan: a binary tree based stream cipher. 573-584 - Peifeng Ni, Zhiyuan Li:
Energy cost analysis of IPSec on handheld devices. 585-594
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2026-02-08 23:06 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
