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ORCIDIEEE Computer Architecture Letters, Volume 18
Volume 18, Number 1, January - June 2019
- Jiho Kim
, Jehee Cha, Jason Jong Kyu Park, Dongsuk Jeon, Yongjun Park:
Improving GPU Multitasking Efficiency Using Dynamic Resource Sharing. 1-5 - Sheng Xu, Xiaoming Chen, Ying Wang, Yinhe Han, Xuehai Qian, Xiaowei Li:
PIMSim: A Flexible and Detailed Processing-in-Memory Simulator. 6-9 - Gil Shomron, Uri C. Weiser:
Spatial Correlation and Value Prediction in Convolutional Neural Networks. 10-13 - Ujjwal Gupta, Sumit K. Mandal, Manqing Mao, Chaitali Chakrabarti, Ümit Y. Ogras:
A Deep Q-Learning Approach for Dynamic Management of Heterogeneous Processors. 14-17 - Samuel Rogers, Joshua Slycord, Ronak Raheja, Hamed Tabkhi:
Scalable LLVM-Based Accelerator Modeling in gem5. 18-21 - Berkin Akin, Alaa R. Alameldeen:
A Case For Asymmetric Processing in Memory. 22-25 - Konstantinos Tovletoglou, Lev Mukhanov, Dimitrios S. Nikolopoulos, Georgios Karakonstantis:
Shimmer: Implementing a Heterogeneous-Reliability DRAM Framework on a Commodity Server. 26-29 - Chanchal Kumar, Sidharth Singh, Gregory T. Byrd:
Hybrid Remote Access Protocol. 30-33 - Yicheng Wang, Yang Liu, Peiyun Wu, Zhao Zhang:
Detect DRAM Disturbance Error by Using Disturbance Bin Counters. 34-37 - Xinfeng Xie, Xing Hu, Peng Gu, Shuangchen Li, Yu Ji, Yuan Xie:
NNBench-X: Benchmarking and Understanding Neural Network Workloads for Accelerator Designs. 38-42 - Asif Ali Khan, Fazal Hameed, Robin Bläsing, Stuart S. P. Parkin, Jerónimo Castrillón:
RTSim: A Cycle-Accurate Simulator for Racetrack Memories. 43-46 - Yiming Gan, Yuxian Qiu, Jingwen Leng, Yuhao Zhu:
SVSoC: Speculative Vision Systems-on-a-Chip. 47-50 - Ting-Ru Lin, Yunfan Li, Massoud Pedram, Lizhong Chen:
Design Space Exploration of Memory Controller Placement in Throughput Processors with Deep Learning. 51-54 - Yehia Arafa, Abdel-Hameed A. Badawy, Gopinath Chennupati, Nandakishore Santhi, Stephan J. Eidenbenz:
PPT-GPU: Scalable GPU Performance Modeling. 55-58 - Bradley Denby, Brandon Lucia:
Orbital Edge Computing: Machine Inference in Space. 59-62 - He Liu, Jianhui Han, Youhui Zhang:
A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration. 63-66 - Tian Tan, Eriko Nurvitadhi, Derek Chiou:
Dark Wires and the Opportunities for Reconfigurable Logic. 67-70 - Ajeya Naithani, Josué Feliu, Almutaz Adileh, Lieven Eeckhout:
Precise Runahead Execution. 71-74 - Varun Agrawal, Mina Abbasi Dinani, Yuxuan Shui, Michael Ferdman, Nima Honarmand:
Massively Parallel Server Processors. 75-78 - Hossein Golestani, Gagan Gupta, Rathijit Sen:
Performance Modeling and Bottleneck Analysis of EDGE Processors Using Dependence Graphs. 79-82 - Jingwen Leng, Alper Buyuktosunoglu, Ramon Bertran, Pradip Bose, Vijay Janapa Reddi:
Asymmetric Resilience for Accelerator-Rich Systems. 83-86
Volume 18, Number 2, July - December 2019
- Elaheh Sadredini, Reza Rahimi, Vaibhav Verma, Mircea Stan, Kevin Skadron:
A Scalable and Efficient In-Memory Interconnect Architecture for Automata Processing. 87-90 - Ahmad Yasin, Avi Mendelson, Yosi Ben-Asher:
Tuning Performance via Metrics with Expectations. 91-94 - Lu Wang, Magnus Jahre, Almutaz Adileh, Zhiying Wang, Lieven Eeckhout:
Modeling Emerging Memory-Divergent GPU Applications. 95-98 - Gil Shomron, Tal Horowitz, Uri C. Weiser:
SMT-SA: Simultaneous Multithreading in Systolic Arrays. 99-102 - Dimosthenis Masouros, Sotirios Xydis, Dimitrios Soudris:
Rusty: Runtime System Predictability Leveraging LSTM Neural Networks. 103-106 - Sunwoong Kim, Hyunmin Jung, Woojae Shin, Hyokeun Lee, Hyuk-Jae Lee:
HAD-TWL: Hot Address Detection-Based Wear Leveling for Phase-Change Memory Systems with Low Latency. 107-110 - Huiyang Zhou, Gregory T. Byrd:
Quantum Circuits for Dynamic Runtime Assertions in Quantum Computation. 111-114 - Jinli Rao, Tianyong Ao, Kui Dai, Xuecheng Zou:
ARCE: Towards Code Pointer Integrity on Embedded Processors Using Architecture-Assisted Run-Time Metadata Management. 115-118 - Kshitij Bhardwaj, Marton Havasi, Yuan Yao, David M. Brooks, José Miguel Hernández-Lobato, Gu-Yeon Wei:
Determining Optimal Coherency Interface for Many-Accelerator SoCs Using Bayesian Optimization. 119-123 - Ali Ansari, Pejman Lotfi-Kamran, Hamid Sarbazi-Azad:
Code Layout Optimization for Near-Ideal Instruction Cache. 124-127 - Kiran Ranganath, AmirAli Abdolrashidi, Shuaiwen Leon Song, Daniel Wong:
Speeding up Collective Communications Through Inter-GPU Re-Routing. 128-131 - Dylan C. Stow, Amin Farmahini Farahani, Sudhanva Gurumurthi, Michael Ignatowski, Yuan Xie:
Power Profiling of Modern Die-Stacked Memory. 132-135 - Seyed Morteza Nabavinejad, Hassan Hafez-Kolahi, Sherief Reda:
Coordinated DVFS and Precision Control for Deep Neural Networks. 136-140 - Seunghak Lee, Nam Sung Kim, Daehoon Kim:
Exploiting OS-Level Memory Offlining for DRAM Power Management. 141-144 - Theodoros Marinakis, Iraklis Anagnostopoulos:
Performance and Fairness Improvement on CMPs Considering Bandwidth and Cache Utilization. 145-148 - Adarsha Balaji, Shihao Song, Anup Das, Nikil D. Dutt, Jeff Krichmar, Nagarajan Kandasamy, Francky Catthoor:
A Framework to Explore Workload-Specific Performance and Lifetime Trade-offs in Neuromorphic Computing. 149-152 - Hyeran Jeon, Hodjat Asghari Esfeden, Nael B. Abu-Ghazaleh, Daniel Wong, Sindhuja Elango:
Locality-Aware GPU Register File. 153-156 - Chen Li, Jun Yang, Yifan Sun, Lingling Jin, Lingjie Xu, Zheng Cao, Pengfei Fan, David R. Kaeli, Sheng Ma, Yang Guo:
Priority-Based PCIe Scheduling for Multi-Tenant Multi-GPU Systems. 157-160 - Jian Weng, Sihao Liu, Vidushi Dadu, Tony Nowatzki:
DAEGEN: A Modular Compiler for Exploring Decoupled Spatial Accelerators. 161-165 - Konstantinos Iliakis, Sotirios Xydis, Dimitrios Soudris:
LOOG: Improving GPU Efficiency With Light-Weight Out-Of-Order Execution. 166-169 - Reoma Matsuo, Ryota Shioya, Hideki Ando:
Improving the Instruction Fetch Throughput with Dynamically Configuring the Fetch Pipeline. 170-173 - Vamsee Reddy Kommareddy, Baogang Zhang, Fan Yao, Rickard Ewetz, Amro Awad:
Are Crossbar Memories Secure? New Security Vulnerabilities in Crossbar Memories. 174-177 - Kristin Barber, Anys Bacha, Li Zhou, Yinqian Zhang, Radu Teodorescu:
Isolating Speculative Data to Prevent Transient Execution Attacks. 178-181
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