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ORCIDDylan C. Stow
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2010 – 2019
- 2019
[j3]Dylan C. Stow
, Amin Farmahini Farahani, Sudhanva Gurumurthi, Michael Ignatowski, Yuan Xie:
Power Profiling of Modern Die-Stacked Memory. IEEE Comput. Archit. Lett. 18(2): 132-135 (2019)- [j2]Itir Akgun, Dylan C. Stow, Yuan Xie:
Network-on-Chip Design Guidelines for Monolithic 3-D Integration. IEEE Micro 39(6): 46-53 (2019) - [c10]Dylan C. Stow, Itir Akgun, Wenqin Huangfu, Yuan Xie, Xueqi Li, Gabriel H. Loh:
Efficient System Architecture in the Era of Monolithic 3D: Dynamic Inter-tier Interconnect and Processing-in-Memory. DAC 2019: 100 - [c9]Dylan C. Stow, Itir Akgun, Yuan Xie:
Investigation of Cost-Optimal Network-on-Chip for Passive and Active Interposer Systems. SLIP 2019: 1-8 - 2018
- [j1]Xing Hu, Dylan C. Stow, Yuan Xie:
Die Stacking Is Happening. IEEE Micro 38(1): 22-28 (2018) - [c8]Peng Gu, Dylan C. Stow, Prashansa Mukim, Shuangchen Li, Yuan Xie:
Cost-efficient 3D Integration to Hinder Reverse Engineering During and After Manufacturing. AsianHOST 2018: 74-79 - 2017
- [c7]Jaya Dofe, Peng Gu, Dylan C. Stow, Qiaoyan Yu, Eren Kursun, Yuan Xie:
Security Threats and Countermeasures in Three-Dimensional Integrated Circuits. ACM Great Lakes Symposium on VLSI 2017: 321-326 - [c6]Dylan C. Stow, Yuan Xie, Taniya Siddiqua, Gabriel H. Loh:
Cost-effective design of scalable high-performance systems using active and passive interposers. ICCAD 2017: 728-735 - 2016
- [c5]Peng Gu, Shuangchen Li, Dylan C. Stow, Russell Barnes, Liu Liu, Yuan Xie, Eren Kursun:
Leveraging 3D Technologies for Hardware Security: Opportunities and Challenges. ACM Great Lakes Symposium on VLSI 2016: 347-352 - [c4]Dylan C. Stow, Itir Akgun, Russell Barnes, Peng Gu, Yuan Xie:
Cost analysis and cost-driven IP reuse methodology for SoC design based on 2.5D/3D integration. ICCAD 2016: 56 - [c3]Peng Gu, Dylan C. Stow, Russell Barnes, Eren Kursun, Yuan Xie:
Thermal-aware 3D design for side-channel information leakage. ICCD 2016: 520-527 - [c2]Dylan C. Stow, Itir Akgun, Russell Barnes, Peng Gu, Yuan Xie:
Cost and Thermal Analysis of High-Performance 2.5D and 3D Integrated Circuit Design Space. ISVLSI 2016: 637-642 - 2012
- [c1]Max A. Korbel, Dylan C. Stow, Chris R. Ferguson, David Money Harris:
Yield-driven minimum energy CMOS cell design. ACSCC 2012: 1010-1014
Coauthor Index
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