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2nd IFMT 2010: Saint-Malo, France

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Hisham El-Shishiny, Erven Rohou:
Proceedings of the Second International Forum on Next-Generation Multicore/Manycore Technologies, IFMT '10, Saint-Malo, France, June 19, 2010. ACM 2010, ISBN 978-1-4503-0008-7

Memory hierarchies for multicore processors

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Kamil Kedzierski, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero:
Power and performance aware reconfigurable cache for CMPs. 1:1-1:12
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Augusto Vega, Alejandro Rico, Felipe Cabarcas, Alex Ramírez, Mateo Valero:
Comparing last-level cache designs for CMP architectures. 2:1-2:11
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Junli Gu, Rakesh Kumar, Steven S. Lumetta, Yihe Sun:
Accelerating data movement on future chip multi-processors. 3:1-3:12
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Abdullah Kayi, Tarek A. El-Ghazawi:
An adaptive cache coherence protocol for chip multiprocessors. 4:1-4:10

Multicore architectures

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Anurag Negi, M. M. Waliullah, Per Stenström:
LV*: a class of lazy versioning HTMs for low-cost integration of transactional memory systems. 5:1-5:10
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Nicolas Ventroux, Raphaël David:
SCMP architecture: an asymmetric multiprocessor system-on-chip for dynamic applications. 6:1-6:12

Parallel programming

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Ahmed El-Mahdy, Hisham El-Shishiny:
Efficient parallel selective separable-kernel convolution on heterogeneous processors. 7:1-7:6
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István Lorentz, Mihaela Malita, Razvan Andonie:
Fitting FFT onto an energy efficient massively parallel architecture. 8:1-8:11

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