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Publication search results
found 250 matches
- 2024
- Mohanan P. R, Mariamma Chacko:
A multi objective DB-RNN based core prediction and resource allocation scheme for multicore processors. Comput. Electr. Eng. 118: 109369 (2024) - Larysa Titarenko, Vyacheslav Kharchenko, Vadym Puidenko, Artem Perepelitsyn, Alexander Barkalov:
Hardware-Based Implementation of Algorithms for Data Replacement in Cache Memory of Processor Cores. Comput. 13(7): 166 (2024) - Alessandro Ottaviano, Robert Balas, Giovanni Bambini, Antonio del Vecchio, Maicol Ciani, Davide Rossi, Luca Benini, Andrea Bartolini:
ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation. Int. J. Parallel Program. 52(1-2): 93-123 (2024) - Jingzhou Li, Huaiyu Chen, Wenbin Zhang, Hu He:
HCRF: A Hardware Checkpoint-based Recovery Framework in light dual-core lockstep processors. ACM Great Lakes Symposium on VLSI 2024: 338-342 - Yuxi Tan, Masaru Nishimura, Riadh Ben Abdelhamid, Bingjie Guo, Qixiang Gao, Yoshiki Yamaguchi:
Systolic Array-Based Many-Core Processor with Simultaneous Dual-Instruction Issuance. HEART 2024: 119-125 - 2023
- Ionel Zagan, Vasile Gheorghita Gaitan:
Custom Soft-Core RISC Processor Validation Based on Real-Time Event Handling Scheduler FPGA Implementation. IEEE Access 11: 36264-36280 (2023) - Osama Ahmed Khashan, Nour Mahmoud Khafajah, Waleed Alomoush, Mohammad Alshinwan, Sultan Alamri, Samer Atawneh, Mutasem K. Alsmadi:
Dynamic Multimedia Encryption Using a Parallel File System Based on Multi-Core Processors. Cryptogr. 7(1): 12 (2023) - Yuan Yao:
Game-of-Life Temperature-Aware DVFS Strategy for Tile-Based Chip Many-Core Processors. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(1): 58-72 (2023) - Khai-Minh Ma, Duc-Hung Le, Cong-Kha Pham, Trong-Thuc Hoang:
Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA. Future Internet 15(5): 186 (2023) - HyungTae Kim, Duk-Yeon Lee, Dongwoon Choi, Jaehyeon Kang, Dong-Wook Lee:
Parallel Implementations of Digital Focus Indices Based on Minimax Search Using Multi-Core Processors. KSII Trans. Internet Inf. Syst. 17(2): 542-558 (2023) - Shreyas Kolala Venkataramanaiah, Jian Meng, Han-Sok Suh, Injune Yeo, Jyotishman Saikia, Sai Kiran Cherupally, Yichi Zhang, Zhiru Zhang, Jae-Sun Seo:
A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity. IEEE J. Solid State Circuits 58(7): 1885-1897 (2023) - Ionel Zagan, Vasile Gheorghita Gaitan:
Soft-core processor integration based on different instruction set architectures and field programmable gate array custom datapath implementation. PeerJ Comput. Sci. 9: e1300 (2023) - An Zou, Yehan Ma, Karthik Garimella, Benjamin Lee, Christopher D. Gill, Xuan Zhang:
F-LEMMA: Fast Learning-Based Energy Management for Multi-/Many-Core Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(2): 616-629 (2023) - Satyam Shukla, Utkarsh, Md Azam, Kailash Chandra Ray:
An Efficient Fault-Tolerant Instruction Decoder for RISC-V Based Dual-Core Soft-Processors. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 4816-4825 (2023) - Tao Liu, Renjiang Chen, Zhaoyuan Liu, Min Tian, Ying Guo, Jingshan Pan:
A Set of New Optimization Methods Based on Sunway Many-core Processor. HP3C 2023: 92-100 - Yibo Zhou, Huabiao Qin, Guancheng Chen:
Intelligent Task Scheduling for Multi-Core Processors Based on Graph Neural Networks and Deep Reinforcement Learning. ICAICE 2023: 875-880 - Sunghoon Hong, Daejin Park:
Differential Image-based Fast and Compatible Convolutional Layers for Multi-core Processors. ICAIIC 2023: 86-90 - Sangyeob Kim, Soyeon Kim, Seongyon Hong, Sangjin Kim, Donghyeon Han, Hoi-Jun Yoo:
C-DNN: A 24.5-85.8TOPS/W Complementary-Deep-Neural-Network Processor with Heterogeneous CNN/SNN Core Architecture and Forward-Gradient-Based Sparsity Generation. ISSCC 2023: 334-335 - Hao Cheng, Chi-Jhe Li, Hung-Lin Chen, Jiun-Lang Huang:
BDD-Based Self-Test Program Generation for Processor Cores. ITC-Asia 2023: 1-6 - Alessandro Ottaviano, Robert Balas, Giovanni Bambini, Antonio del Vecchio, Maicol Ciani, Davide Rossi, Luca Benini, Andrea Bartolini:
ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation. CoRR abs/2306.09501 (2023) - Xin Chen, Yucheng Ouyang, Xin Chen, Zhenchuan Chen, Rongfen Lin, Xingyu Gao, Lifang Wang, Fang Li, Yin Liu, Honghui Shang, Haifeng Song:
TensorMD: Scalable Tensor-Diagram based Machine Learning Interatomic Potential on Heterogeneous Many-Core Processors. CoRR abs/2310.08439 (2023) - 2022
- Ahmed Kamaleldin, Diana Göhringer:
AGILER: An Adaptive Heterogeneous Tile-Based Many-Core Architecture for RISC-V Processors. IEEE Access 10: 43895-43913 (2022) - Marcel Mettler, Martin Rapp, Heba Khdr, Daniel Mueller-Gritschneder, Jörg Henkel, Ulf Schlichtmann:
An FPGA-based Approach to Evaluate Thermal and Resource Management Strategies of Many-core Processors. ACM Trans. Archit. Code Optim. 19(3): 31:1-31:24 (2022) - Hao Cao, Shaozhong Guo, Jiangwei Hao, Yuanyuan Xia, Jinchen Xu:
Superblock-based performance optimization for Sunway Math Library on SW26010 many-core processor. J. Supercomput. 78(4): 4827-4849 (2022) - Shreyas Kolala Venkataramanaiah, Jian Meng, Han-Sok Suh, Injune Yeo, Jyotishman Saikia, Sai Kiran Cherupally, Yichi Zhang, Zhiru Zhang, Jae-sun Seo:
A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation/Weight Sparsification. ESSCIRC 2022: 89-92 - Mohammad Samadi Gharajeh, Sara Royuela, Luís Miguel Pinho, Tiago Carvalho, Eduardo Quiñones:
Heuristic-based Task-to-Thread Mapping in Multi-Core Processors. ETFA 2022: 1-4 - 2021
- Rohan Tabish:
Next-generation safety-critical systems using COTS based homogeneous multi-core processors and heterogeneous MPSoCS. University of Illinois Urbana-Champaign, USA, 2021 - Jiajun Wu, Xuan Huang, Le Yang, Jipeng Wang, Bingqiang Liu, Ziyuan Wen, Juhui Li, Guoyi Yu, Kwen-Siong Chong, Chao Wang:
An Energy-Efficient Deep Belief Network Processor Based on Heterogeneous Multi-Core Architecture With Transposable Memory and On-Chip Learning. IEEE J. Emerg. Sel. Topics Circuits Syst. 11(4): 725-738 (2021) - Haider Muhi Abbas, Basel Halak, Mark Zwolinski:
Learning-based BTI stress estimation and mitigation in multi-core processor systems. Microprocess. Microsystems 81: 103713 (2021) - Yisi Liu, Gaowei Zhao:
Simulation of swimming sports image recognition based on multi-core processor and dynamic image sampling. Microprocess. Microsystems 81: 103753 (2021)
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