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Books and Theses
- 1976
[b1]William H. Kao:
Computer-Aided Analysis of Mixer Circuits. University of Illinois Urbana-Champaign, USA, 1976
Journal Articles
- 2001
- [j1]William H. Kao, Chi-Yuan Lo, Mark Basel, Raminderpal Singh:
Parasitic extraction: current state of the art and future trends. Proc. IEEE 89(5): 729-739 (2001)
Conference and Workshop Papers
- 2007
- [c12]William H. Kao, Xiaopeng Dong:
Digital Block Modeling and Substrate Noise Aware Floorplanning for Mixed Signal SOCs. ISCAS 2007: 1935-1938 - 2003
- [c11]William H. Kao, Wenkung K. Chu:
Noise constraint driven placement for mixed signal designs. ISCAS (4) 2003: 712-715 - 2001
- [c10]Wenting Hou, Hong Yu, Xianlong Hong, Yici Cai, Weimin Wu, Jun Gu, William H. Kao:
A new congestion-driven placement algorithm based on cell inflation. ASP-DAC 2001: 605-608 - [c9]William H. Kao, Chi-Yuan Lo, Raminderpal Singh, Mark Basel:
Parasitic extraction: current state of the art and future trends. ISCAS (5) 2001: 487-490 - 1999
- [c8]Junwei Hou, William H. Kao, Abhijit Chatterjee:
A novel concurrent fault simulation method for mixed-signal circuits. ISCAS (2) 1999: 448-451 - 1998
- [c7]Bogdan G. Arsintescu, Edoardo Charbon, Enrico Malavasi, Umakanta Choudhury, William H. Kao:
General AC Constraint Transformation for Analog ICs. DAC 1998: 38-43 - [c6]Enrico Malavasi, Edoardo Charbon, Bogdan G. Arsintescu, William H. Kao:
A Constraint Management System for IC Physical Design. SBCCI 1998: 240-243 - 1997
- [c5]Ramakrishna Voorakaranam, Sudip Chakrabarti, Junwei Hou, Alfred V. Gomes, Sasikumar Cherubal, Abhijit Chatterjee, William H. Kao:
Hierarchical Specification-Driven Analog Fault Modeling for Efficient Fault Simulation and Diagnosis. ITC 1997: 903-912 - 1993
- [c4]William H. Kao, Jean Qincui Xia:
Automatic synthesis of DUT board circuits for testing of mixed signal ICs. VTS 1993: 230-236 - 1992
- [c3]Stephen C. Bateman, William H. Kao:
Simulation of an Integrated Design and Test Environment for Mixed-Signal Integrated Circuits. ITC 1992: 405-414 - 1985
- [c2]William H. Kao, Nader Fathi, Chia-Hao Lee:
Algorithms for automatic transistor sizing in CMOS digital circuits. DAC 1985: 781-784 - 1984
- [c1]William H. Kao, Mohammad H. Movahed-Ezazi, Mark L. Sabiers:
ARIES: A workstation based, schematic driven system for circuit design. DAC 1984: 301-307
Coauthor Index
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