Takahiro J. Yamaguchi

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Masato Sakurai

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Publications

2013
[c48]
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Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Masato Sakurai, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi:
Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges. ASP-DAC 2013: 103-104
2012
[j7]
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Kiichi Niitsu, Masato Sakurai, Naohiro Harigai, Takahiro J. Yamaguchi, Haruo Kobayashi:
CMOS Circuits to Measure Timing Jitter Using a Self-Referenced Clock and a Cascaded Time Difference Amplifier With Duty-Cycle Compensation. IEEE J. Solid State Circuits 47(11): 2701-2710 (2012)
[c42]
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Kiichi Niitsu, Masato Sakurai, Naohiro Harigai, Daiki Hirabayashi, Takahiro J. Yamaguchi, Haruo Kobayashi:
A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOS. ASP-DAC 2012: 553-554
[c38]
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Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Masato Sakurai, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi:
A clock jitter reduction circuit using gated phase blending between self-delayed clock edges. VLSIC 2012: 142-143
2011
[c37]
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Kiichi Niitsu, Masato Sakurai, Naohiro Harigai, Takahiro J. Yamaguchi, Haruo Kobayashi:
An on-chip timing jitter measurement circuit using a self-referenced clock and a cascaded time difference amplifier with duty-cycle compensation. A-SSCC 2011: 201-204
[c34]
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Masato Sakurai, Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Takahiro J. Yamaguchi, Haruo Kobayashi:
Analysis of jitter accumulation in interleaved phase frequency detectors for high-accuracy on-chip jitter measurements. ISOCC 2011: 146-149

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