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Xinyu Niu
Publications
- 2023
- [j18]Hongxiang Fan, Shuanglong Liu, Zhiqiang Que, Xinyu Niu, Wayne Luk:
High-Performance Acceleration of 2-D and 3-D CNNs on FPGAs Using Static Block Floating Point. IEEE Trans. Neural Networks Learn. Syst. 34(8): 4473-4487 (2023) - 2022
- [j16]Hongxiang Fan, Martin Ferianc, Zhiqiang Que, Shuanglong Liu, Xinyu Niu, Miguel R. D. Rodrigues, Wayne Luk:
FPGA-Based Acceleration for Bayesian Convolutional Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5343-5356 (2022) - [j15]Shuanglong Liu, Hongxiang Fan, Martin Ferianc, Xinyu Niu, Huifeng Shi, Wayne Luk:
Toward Full-Stack Acceleration of Deep Convolutional Neural Networks on FPGAs. IEEE Trans. Neural Networks Learn. Syst. 33(8): 3974-3987 (2022) - [c49]Hongxiang Fan, Martin Ferianc, Zhiqiang Que, He Li, Shuanglong Liu, Xinyu Niu, Wayne Luk:
Algorithm and Hardware Co-design for Reconfigurable CNN Accelerator. ASP-DAC 2022: 250-255 - 2021
- [i3]Hongxiang Fan, Martin Ferianc, Zhiqiang Que, He Li, Shuanglong Liu, Xinyu Niu, Wayne Luk:
Algorithm and Hardware Co-design for Reconfigurable CNN Accelerator. CoRR abs/2111.12787 (2021) - 2020
- [c46]Hongxiang Fan, Martin Ferianc, Shuanglong Liu, Zhiqiang Que, Xinyu Niu, Wayne Luk:
Optimizing FPGA-Based CNN Accelerator Using Differentiable Neural Architecture Search. ICCD 2020: 465-468 - 2019
- [c42]Hongxiang Fan, Cheng Luo, Chenglong Zeng, Martin Ferianc, Zhiqiang Que, Shuanglong Liu, Xinyu Niu, Wayne Luk:
F-E3D: FPGA-based Acceleration of an Efficient 3D Convolutional Neural Network for Human Action Recognition. ASAP 2019: 1-8 - [c41]Zhiqiang Que, Thomas Nugent, Shuanglong Liu, Li Tian, Xinyu Niu, Yongxin Zhu, Wayne Luk:
Efficient Weight Reuse for Large LSTMs. ASAP 2019: 17-24 - 2018
- [j8]Shuanglong Liu, Hongxiang Fan, Xinyu Niu, Ho-Cheung Ng, Yang Chu, Wayne Luk:
Optimizing CNN-based Segmentation with Deeply Customized Convolutional and Deconvolutional Architectures on FPGA. ACM Trans. Reconfigurable Technol. Syst. 11(3): 19:1-19:22 (2018) - [c38]Ruizhe Zhao, Shuanglong Liu, Ho-Cheung Ng, Erwei Wang, James J. Davis, Xinyu Niu, Xiwei Wang, Huifeng Shi, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Hardware Compilation of Deep Neural Networks: An Overview. ASAP 2018: 1-8 - [c36]Shuanglong Liu, Xinyu Niu, Wayne Luk:
A Low-Power Deconvolutional Accelerator for Convolutional Neural Network Based Segmentation on FPGA: Abstract Only. FPGA 2018: 293 - [c34]Hongxiang Fan, Ho-Cheung Ng, Shuanglong Liu, Zhiqiang Que, Xinyu Niu, Wayne Luk:
Reconfigurable Acceleration of 3D-CNNs for Human Action Recognition with Block Floating-Point Representation. FPL 2018: 287-294 - [c33]Hongxiang Fan, Shuanglong Liu, Martin Ferianc, Ho-Cheung Ng, Zhiqiang Que, Shen Liu, Xinyu Niu, Wayne Luk:
A Real-Time Object Detection Accelerator with Compressed SSDLite on FPGA. FPT 2018: 14-21 - [c32]Shuanglong Liu, Chenglong Zeng, Hongxiang Fan, Ho-Cheung Ng, Jiuxi Meng, Zhiqiang Que, Xinyu Niu, Wayne Luk:
Memory-Efficient Architecture for Accelerating Generative Networks on FPGA. FPT 2018: 30-37
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