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Publications
- 2022
[c74]Yasong Cao, Mei Wen, Junzhong Shen, Sheng Liu, Zhi Wang, Minjin Tang, Yahao Fang, Jianchao Yang, Renyu Yang, Yuhan Kang, Jiawei Fei:
MZ Core: An Enhanced Matrix Acceleration Engine for HPC/ AI Applications. HPCC/DSS/SmartCity/DependSys 2022: 126-134- [c71]Jianchao Yang, Mei Wen, Junzhong Shen, Yasong Cao, Minjin Tang, Renyu Yang, Jiawei Fei, Chunyuan Zhang:
BP-Im2col: Implicit Im2col Supporting AI Backpropagation on Systolic Arrays. ICCD 2022: 415-418 - [c70]Minjin Tang, Mei Wen, Yasong Cao, Junzhong Shen, Jianchao Yang, Jiawei Fei, Yang Guo, Sheng Liu:
Mentha: Enabling Sparse-Packing Computation on Systolic Arrays. ICPP 2022: 18:1-18:11 - [c69]Yuhang Li, Mei Wen, Renyu Yang, Junzhong Shen, Yasong Cao, Jianan Wang:
S-SIM: A Simulator for Systolic Array-based DNN Accelerators with Tile Access Awareness. ISCAS 2022: 2720-2724 - [c68]Yuhang Li, Mei Wen, Jiawei Fei, Junzhong Shen, Yasong Cao:
TILE-SIM: A Systematic Approach to Systolic Array-based Accelerator Evaluation. ISPASS 2022: 141-143 - [i4]Jianchao Yang, Mei Wen, Junzhong Shen, Yasong Cao, Minjin Tang, Renyu Yang, Jiawei Fei, Chunyuan Zhang:
BP-Im2col: Implicit Im2col Supporting AI Backpropagation on Systolic Arrays. CoRR abs/2209.09434 (2022) - 2021
- [c67]Renyu Yang, Junzhong Shen, Mei Wen, Yasong Cao, Yuhang Li:
Embrace the Conflicts: Exploring the Integration of Single Port Memory in Systolic Array-based Accelerators. HPCC/DSS/SmartCity/DependSys 2021: 133-140 - [c66]Jianchao Yang, Mei Wen, Minjin Tang, Junzhong Shen, Chunyuan Zhang:
SAI: Self-Adjusting Incremental Quantile Estimation for Sparse Training of Neural Networks on Hardware Accelerators. HPCC/DSS/SmartCity/DependSys 2021: 1049-1058 - 2020
- [j27]Zhuang Cao
, Huayou Su, Qianming Yang, Junzhong Shen, Mei Wen, Chunyuan Zhang:
P4 to FPGA-A Fast Approach for Generating Efficient Network Processors. IEEE Access 8: 23440-23456 (2020) - [j25]Junzhong Shen, You Huang, Mei Wen, Chunyuan Zhang:
Toward an Efficient Deep Pipelined Template-Based Architecture for Accelerating the Entire 2-D and 3-D CNNs on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(7): 1442-1455 (2020) - [c63]Minjin Tang, Mei Wen, Junzhong Shen, Xiaolei Zhao, Chunyuan Zhang:
Towards Memory-Efficient Streaming Processing with Counter-Cascading Sketching on FPGA. DAC 2020: 1-6 - [c62]Junzhong Shen, Mei Wen, Minjin Tang, Xiaolei Zhao, Chunyuan Zhang:
Scalable FPGA-based Architecture for High-Performance Per-Flow Traffic Measurement. FPGA 2020: 315 - [c61]Qixuan Cheng, Mei Wen, Junzhong Shen, Deguang Wang, Chunyuan Zhang:
Towards a Deep-Pipelined Architecture for Accelerating Deep GCN on a Multi-FPGA Platform. ICA3PP (1) 2020: 528-547 - 2019
- [c56]Junzhong Shen, Deguang Wang, You Huang, Mei Wen, Chunyuan Zhang:
Scale-out Acceleration for 3D CNN-based Lung Nodule Segmentation on a Multi-FPGA System. DAC 2019: 207 - [c54]Junzhong Shen, Deguang Wang, You Huang, Mei Wen, Chunyuan Zhang:
Accelerating 3D CNN-based Lung Nodule Segmentation on a Multi-FPGA System. FPGA 2019: 117 - [c49]Deguang Wang, Junzhong Shen, Mei Wen, Chunyuan Zhang:
An Efficient Design Flow for Accelerating Complicated-connected CNNs on a Multi-FPGA Platform. ICPP 2019: 98:1-98:10 - [c46]Deguang Wang, Junzhong Shen, Mei Wen, Chunyuan Zhang:
Towards a Uniform Architecture for the Efficient Implementation of 2D and 3D Deconvolutional Neural Networks on FPGAs. ISCAS 2019: 1-5 - [i2]Deguang Wang, Junzhong Shen, Mei Wen, Chunyuan Zhang:
Towards a Uniform Architecture for the Efficient Implementation of 2D and 3D Deconvolutional Neural Networks on FPGAs. CoRR abs/1903.02550 (2019) - 2018
- [j20]You Huang, Junzhong Shen, Yuran Qiao, Mei Wen, Chunyuan Zhang:
MALMM: A multi-array architecture for large-scale matrix multiplication on FPGA. IEICE Electron. Express 15(10): 20180286 (2018) - [c44]Junzhong Shen, You Huang, Zelong Wang, Yuran Qiao, Mei Wen, Chunyuan Zhang:
Towards a Uniform Template-based Architecture for Accelerating 2D and 3D CNNs on FPGA. FPGA 2018: 97-106 - [c41]Junzhong Shen, Yuran Qiao, You Huang, Mei Wen, Chunyuan Zhang:
Towards a Multi-array Architecture for Accelerating Large-scale Matrix Multiplication on FPGAs. ISCAS 2018: 1-5 - [i1]Junzhong Shen, Yuran Qiao, You Huang, Mei Wen, Chunyuan Zhang:
Towards a Multi-array Architecture for Accelerating Large-scale Matrix Multiplication on FPGAs. CoRR abs/1803.03790 (2018) - 2017
- [j17]Yuran Qiao, Junzhong Shen, Tao Xiao, Qianming Yang, Mei Wen, Chunyuan Zhang:
FPGA-accelerated deep convolutional neural networks for high throughput and energy efficiency. Concurr. Comput. Pract. Exp. 29(20) (2017) - [c39]Yuran Qiao, Junzhong Shen, Dafei Huang, Qianming Yang, Mei Wen, Chunyuan Zhang:
Optimizing OpenCL Implementation of Deep Convolutional Neural Network on FPGA. NPC 2017: 100-111 - 2015
- [c36]Tao Xiao, Yuran Qiao, Junzhong Shen, Qianming Yang, Mei Wen:
Unified Virtual Memory Support for Deep CNN Accelerator on SoC FPGA. ICA3PP (1) 2015: 64-76
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last updated on 2024-05-09 00:23 CEST by the dblp team
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