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ORCIDNaoya Onizawa
- > Home > Persons > Naoya Onizawa
Publications
- 2014
[j13]Naoya Onizawa, Atsushi Matsumoto, Tomoyoshi Funazaki, Takahiro Hanyu:
High-Throughput Compact Delay-Insensitive Asynchronous NoC Router. IEEE Trans. Computers 63(3): 637-649 (2014)- 2013
- [j8]Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu:
Open-Fault Resilient Multiple-Valued Codes for Reliable Asynchronous Global Communication Links. IEICE Trans. Inf. Syst. 96-D(9): 1952-1961 (2013) - 2012
- [j7]Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu:
Long-Range Asynchronous On-Chip Link Based on Multiple-Valued Single-Track Signaling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(6): 1018-1029 (2012) - [c15]Atsushi Matsumoto, Naoya Onizawa, Takahiro Hanyu:
Systematic Coding Schemes for Low-Power Multiple-Valued Current-Mode Asynchronous Communication Links. ISMVL 2012: 13-18 - [c13]Tomohiro Yoneda, Masashi Imai, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu:
Multi-chip NoCs for Automotive Applications. PRDC 2012: 105-110 - 2011
- [c11]Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu:
Interconnect-fault-resilient delay-insensitive asynchronous communication link based on current-flow monitoring. DATE 2011: 776-781 - [c10]Takao Kawano, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu:
Adjacent-State monitoring based fine-grained power-gating scheme for a low-power asynchronous pipelined system. ISCAS 2011: 2067-2070 - [c9]Atsushi Matsumoto, Naoya Onizawa, Takahiro Hanyu:
Complementary Multiple-Valued Encoding Scheme for Interconnect-Fault-Resilient Bidirectional Asynchronous Links. ISMVL 2011: 236-241 - 2010
- [c7]Atsushi Matsumoto, Naoya Onizawa, Takahiro Hanyu:
One-Color Two-Phase Asynchronous Communication Links Based on Multiple-Valued Simultaneous Control. ISMVL 2010: 211-216 - [c6]Naoya Onizawa, Tomoyoshi Funazaki, Atsushi Matsumoto, Takahiro Hanyu:
Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model. ISVLSI (Selected papers) 2010: 17-30 - [c5]Naoya Onizawa, Tomoyoshi Funazaki, Atsushi Matsumoto, Takahiro Hanyu:
Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model. ISVLSI 2010: 357-362
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