Ricardo Augusto da Luz Reis

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with José Monteiro 0001

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Publications

2019
[e20]
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  - conf/vlsi/2017socs
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Michail Maniatakos, Ibrahim Abe M. Elfadel, Matteo Sonza Reorda, H. Fatih Ugurdag, José Monteiro, Ricardo Reis:
VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things - 25th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017, Revised and Extended Selected Papers. IFIP Advances in Information and Communication Technology 500, Springer 2019, ISBN 978-3-030-15662-6 [contents]
2012
[c134]
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  - conf/icecsys/GhissoniCMR12
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Sidinei Ghissoni, Eduardo Costa, José Monteiro, Ricardo Reis:
Efficient area and power multiplication part of FFT based on twiddle factor decomposition. ICECS 2012: 657-660
2011
[c128]
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Sidinei Ghissoni, Eduardo Costa, José Monteiro, Ricardo Reis:
Combination of constant matrix multiplication and gate-level approaches for area and power efficient hybrid radix-2 DIT FFT realization. ICECS 2011: 567-570
2010
[c117]
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  - conf/icecsys/GhissoniCLMAR10
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Sidinei Ghissoni, Eduardo Costa, Cristiano Lazzari, José Monteiro, Levent Aksoy, Ricardo Reis:
Radix-2 Decimation in Time (DIT) FFT implementation based on a Matrix-Multiple Constant multiplication approach. ICECS 2010: 859-862
2009
[c101]
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  - conf/patmos/GhissoniMRM09
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Sidinei Ghissoni, João Baptista dos Santos Martins, Ricardo Augusto da Luz Reis, José C. Monteiro:
Analysis of Power Consumption Using a New Methodology for the Capacitance Modeling of Complex Logic Gates. PATMOS 2009: 297-306
2005
[c57]
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  - conf/vlsi/OliveiraSFCMMBR05
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Leonardo Londero de Oliveira, Cristiano Santos, Daniel Lima Ferrão, Eduardo A. C. da Costa, José Monteiro, João Baptista dos Santos Martins, Sergio Bampi, Ricardo Augusto da Luz Reis:
A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures. VLSI-SoC 2005: 25-39

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