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Takahiro Watanabe
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Publications
- 2013
- [c27]Takashi Yoza, Retsu Moriwaki, Yuki Torigai, Yuki Kamikubo, Takayuki Kubota, Takahiro Watanabe, Takumi Fujimori, Hiroyuki Ito, Masato Seo, Kouta Akagi, Yuichiro Yamaji, Minoru Watanabe:
FPGA Blokus Duo Solver using a massively parallel architecture. FPT 2013: 494-497 - 2012
- [j17]Takahiro Watanabe, Minoru Watanabe:
0.18 μm CMOS proess high-sensitivity optially reonfgurable gatearray VLSI. SIGARCH Comput. Archit. News 40(5): 82-86 (2012) - [c26]Takahiro Watanabe, Minoru Watanabe:
Triple Module Redundancy of a Laser Array Driver Circuit for Optically Reconfigurable Gate Arrays. ARC 2012: 163-173 - [c25]Takahiro Watanabe, Minoru Watanabe:
High Speed - Low Power Optical Configuration on an ORGA with a Phase-modulation Type Holographic Memory. IPDPS Workshops 2012: 256-260 - [c24]Takahiro Watanabe, Minoru Watanabe:
0.18-um CMOS Process Highly Sensitive Differential Optically Reconfigurable Gate Array VLSI. ISVLSI 2012: 308-313 - [c23]Takahiro Watanabe, Minoru Watanabe:
Inversion/non-inversion reconfiguration scheme for a 0.18 J.1m CMOS process optically reconfigurable gate array VLSI. MWSCAS 2012: 117-120 - 2011
- [c20]Takahiro Watanabe, Minoru Watanabe:
Dependable Optically Reconfigurable Gate Array with a Phase-Modulation Type Holographic Memory. FPL 2011: 34-37 - [c19]Takahiro Watanabe, Retsu Moriwaki, Yuichiro Yamaji, Yuki Kamikubo, Yuki Torigai, Yuki Nihira, Takashi Yoza, Yumiko Ueno, Yuji Aoyama, Minoru Watanabe:
An FPGA Connect6 Solver with a two-stage pipelined evaluation. FPT 2011: 1-4 - 2010
- [c14]Takayuki Mabuchi, Takahiro Watanabe, Retsu Moriwaki, Yuji Aoyama, Amarjargal Gundjalam, Yuichiro Yamaji, Hironari Nakada, Minoru Watanabe:
Othello Solver based on a soft-core MIMD processor array. FPT 2010: 511-514
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