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Wu-Shiung Feng
- > Home > Persons > Wu-Shiung Feng
Publications
- 2000
- [j9]Cheng-Chung Hsu, Wu-Shiung Feng:
Testable design of multiple-stage OTA-C filters. IEEE Trans. Instrum. Meas. 49(5): 929-934 (2000) - 1994
- [j7]Jyh-Ming Wang, Sung-Chuan Fang, Wu-Shiung Feng:
New efficient designs for XOR and XNOR functions on the transistor level. IEEE J. Solid State Circuits 29(7): 780-786 (1994) - 1992
- [j6]Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng:
An H-V alternating router. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(8): 976-991 (1992) - [c5]Sung-Chuan Fang, Wu-Shiung Feng, Shian-Lang Lee:
A New Efficient Approach to Multilayer Channel Routing Problem. DAC 1992: 579-584 - 1991
- [j5]Pei-Yung Hsiao, S. F. Steven Chen, Chia-Chun Tsai, Wu-Shiung Feng:
A knowledge-based program for compacting mask layout of integrated circuits. Comput. Aided Des. 23(3): 223-231 (1991) - [c4]Sung-Chuan Fang, Kuo-En Chang, Wu-Shiung Feng, Sao-Jie Chen:
Constrained via Minimization with Practical Considerations for Multi-Layer VLSI/PCB Routing Problems. DAC 1991: 60-65 - 1990
- [j4]Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng:
Generalized terminal connectivity problem for multilayer layout scheme. Comput. Aided Des. 22(7): 423-433 (1990) - [j3]Pei-Yung Hsiao, H. F. Steven Chen, Wu-Shiung Feng:
A new control strategy for an artificial intelligence approach to VLSI layout compaction. Integr. 10(1): 55-70 (1990) - [j2]Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng:
An H-V Tile-Expansion Router. J. Inf. Sci. Eng. 6(3): 173-189 (1990) - [j1]Pei-Yung Hsiao, Wu-Shiung Feng:
Using a multiple storage quad tree on a hierarchical VLSI compaction scheme. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(5): 522-536 (1990) - 1989
- [c2]S. F. Steven Chen, Pei-Yung Hsiao, Wu-Shiung Feng, Shun-Nan Dai, Wen-Zyh Wang:
The Control Model for a Knowledge-Based Approach to VLSI Compaction Design. IFIP Congress 1989: 241-246 - 1988
- [c1]Pei-Yung Hsiao, Chen Yung Syau, Wu-Shiung Feng, T. M. Parng, Cheng-Chung Hsu:
A rule-based compactor for VLSI/CAD mask layout. COMPSAC 1988: 35-42
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