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ORCIDDaniel Grund
Person information
- affiliation: Thales Transportation Systems, Stuttgart, Germany
- affiliation: Saarland University, Department of Computer Science, Saarbrücken, Germany
- affiliation: Fraunhofer Institute for Open Communication Systems (FOKUS), Berlin, Germany
- affiliation: University of Karlsruhe, Germany
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2010 – 2019
- 2014
[j6]Reinhard Wilhelm, Daniel Grund:
Computation takes time, but how much? Commun. ACM 57(2): 94-103 (2014)- [j5]Philip Axer, Rolf Ernst, Heiko Falk, Alain Girault, Daniel Grund, Nan Guan
, Bengt Jonsson, Peter Marwedel, Jan Reineke, Christine Rochange, Maurice Sebastian, Reinhard von Hanxleden, Reinhard Wilhelm, Wang Yi:
Building timing predictable embedded systems. ACM Trans. Embed. Comput. Syst. 13(4): 82:1-82:37 (2014) - [c16]Jan Reineke, Sebastian Altmeyer, Daniel Grund, Sebastian Hahn, Claire Maiza:
Selfish-LRU: Preemption-aware caching for predictability and performance. RTAS 2014: 135-144 - 2013
- [j4]Jan Reineke, Daniel Grund:
Sensitivity of cache replacement policies. ACM Trans. Embed. Comput. Syst. 12(1s): 42:1-42:18 (2013) - 2012
- [c15]Sebastian Hahn, Daniel Grund:
Relational Cache Analysis for Static Timing Analysis. ECRTS 2012: 102-111 - 2011
- [j3]Daniel Grund, Jan Reineke, Gernot Gebhard:
Branch target buffers: WCET analysis framework and timing predictability. J. Syst. Archit. 57(6): 625-637 (2011) - [c14]Daniel Grund, Jan Reineke, Reinhard Wilhelm:
A Template for Predictability Definitions with Supporting Evidence. PPES 2011: 22-31 - 2010
- [c13]Daniel Grund, Jan Reineke:
Precise and Efficient FIFO-Replacement Analysis Based on Static Phase Detection. ECRTS 2010: 155-164 - [c12]Reinhard Wilhelm, Sebastian Altmeyer, Claire Burguière, Daniel Grund, Jörg Herter, Jan Reineke, Björn Wachter, Stephan Wilhelm:
Static Timing Analysis for Hard Real-Time Systems. VMCAI 2010: 3-22 - [c11]Daniel Grund, Jan Reineke:
Toward Precise PLRU Cache Analysis. WCET 2010: 23-35
2000 – 2009
- 2009
- [j2]Reinhard Wilhelm, Daniel Grund, Jan Reineke, Marc Schlickling, Markus Pister, Christian Ferdinand:
Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-Critical Embedded Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(7): 966-978 (2009) - [c10]Daniel Grund, Jan Reineke, Gernot Gebhard:
Branch Target Buffers: WCET Analysis Framework and Timing Predictability. RTCSA 2009: 3-12 - [c9]Daniel Grund, Jan Reineke:
Abstract Interpretation of FIFO Replacement. SAS 2009: 120-136 - 2008
- [c8]Benoit Boissinot, Sebastian Hack, Daniel Grund, Benoît Dupont de Dinechin, Fabrice Rastello:
Fast liveness checking for ssa-form programs. CGO 2008: 35-44 - [c7]Jan Reineke, Daniel Grund:
Relative competitive analysis of cache replacement policies. LCTES 2008: 51-60 - [c6]Daniel Grund, Jan Reineke:
Estimating the Performance of Cache Replacement Policies. MEMOCODE 2008: 101-112 - [c5]Jan Reineke, Daniel Grund:
Relative competitiveness of cache replacement policies. SIGMETRICS 2008: 431-432 - 2007
- [j1]Jan Reineke, Daniel Grund, Christoph Berg, Reinhard Wilhelm:
Timing predictability of cache replacement policies. Real Time Syst. 37(2): 99-122 (2007) - [c4]Daniel Grund, Sebastian Hack:
A Fast Cutting-Plane Algorithm for Optimal Coalescing. CC 2007: 111-125 - [c3]Tibor Farkas, Daniel Grund:
Rule Checking within the Model-Based Development of Safety-Critical Systems and Embedded Automotive Software. ISADS 2007: 287-294 - 2006
- [c2]Sebastian Hack, Daniel Grund, Gerhard Goos:
Register Allocation for Programs in SSA-Form. CC 2006: 247-262 - [c1]Rubino Geiß, Gernot Veit Batz, Daniel Grund, Sebastian Hack, Adam Szalkowski:
GrGen: A Fast SPO-Based Graph Rewriting Tool. ICGT 2006: 383-397
Coauthor Index
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