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ORCID20th RTAS 2014: Berlin, Germany
- 20th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2014, Berlin, Germany, April 15-17, 2014. IEEE Computer Society 2014, ISBN 978-1-4799-4691-4
- Richard West, James H. Anderson, Samarjit Chakraborty
:
Message from the Program and Track Chairs. ix-x
Software Architectures and Systems
- Rafia Inam, Nesredin Mahmud, Moris Behnam, Thomas Nolte, Mikael Sjödin:
The Multi-Resource Server for predictable execution on multi-core platforms. 1-12 - Stefan Groesbrink, Luís Almeida, Mário de Sousa, Stefan M. Petters:
Towards certifiable adaptive reservations for hypervisor-based virtualization. 13-24 - Qi Wang, Gabriel Parmer:
FJOS: Practical, predictable, and efficient system support for fork/join parallelism. 25-36 - Daniel Danner, Rainer Muller, Wolfgang Schröder-Preikschat, Wanja Hofer, Daniel Lohmann:
SAFER SLOTH: Efficient, hardware-tailored memory protection. 37-48
Scheduling I
- Robert I. Davis, Timo Feld, Victor Pollex, Frank Slomka:
Schedulability tests for tasks with Variable Rate-dependent Behaviour under fixed priority scheduling. 51-62 - Mohammad A. Haque, Hakan Aydin, Dakai Zhu:
Real-time scheduling under fault bursts with multiple recovery strategy. 63-74 - Saud Wasly, Rodolfo Pellizzoni:
Hiding memory latency using fixed priority scheduling. 75-86
Mixed Criticality Systems
- Eugene Yip, Matthew M. Y. Kuo, Partha S. Roop, David Broman:
Relaxing the synchronous approach for mixed-criticality systems. 89-100 - Michael Zimmer, David Broman, Chris Shaver, Edward A. Lee:
FlexPRET: A processor platform for mixed-criticality systems. 101-110 - Dionisio de Niz, Linh T. X. Phan:
Partitioned scheduling of multi-modal mixed-criticality real-time systems on multiprocessor platforms. 111-122
Memory and Cache Management
- Kartik Nagar, Y. N. Srikant:
Precise shared cache analysis using optimal interference placement. 125-134 - Jan Reineke, Sebastian Altmeyer, Daniel Grund, Sebastian Hahn, Claire Maiza:
Selfish-LRU: Preemption-aware caching for predictability and performance. 135-144 - Hyoseung Kim, Dionisio de Niz, Björn Andersson, Mark H. Klein, Onur Mutlu, Ragunathan Rajkumar:
Bounding memory interference delay in COTS-based multi-core systems. 145-154 - Heechul Yun, Renato Mancuso, Zheng Pei Wu, Rodolfo Pellizzoni:
PALLOC: DRAM bank-aware memory allocator for performance isolation on multicore platforms. 155-166
Timing Analysis
- Bernard Blackham, Mark H. Liffiton, Gernot Heiser:
Trickle: Automated infeasible path detection using all minimal unsatisfiable subsets. 169-178 - Yooseong Kim, David Broman, Jian Cai, Aviral Shrivastava:
WCET-aware dynamic code management on scratchpads for Software-Managed Multicores. 179-188 - Jan Reineke, Johannes Doerfert:
Architecture-parametric timing analysis. 189-200
Hardware-Software Interaction
- Daniel Lo, Mohamed Ismail, Tao Chen, G. Edward Suh:
Slack-aware opportunistic monitoring for real-time systems. 203-214 - Christian Herber, Andre Oliver Richter, Thomas Wild, Andreas Herkersdorf:
A network virtualization approach for performance isolation in controller area network (CAN). 215-224 - Javier Jalle, Jaume Abella, Eduardo Quiñones, Luca Fossati, Marco Zulianello, Francisco J. Cazorla:
AHRB: A high-performance time-composable AMBA AHB bus. 225-236 - Sriram Karunagaran, Karuna P. Sahoo, Jayaraj Poroor, Masahiro Fujita:
MAESTRO: A time-driven embedded testbed Architecture with Event-driven Synchronization. 237-248
Scheduling II
- Risat Mahmud Pathan, Per Stenström, Lars-Goran Green, Torbjorn Hult, Patrik Sandin:
Overhead-aware temporal partitioning on multicore processors. 251-262 - Felipe Cerqueira, Manohar Vanga, Björn B. Brandenburg:
Scaling global scheduling with message passing. 263-274 - Marcus Völp, Marcus Hähnel, Adam Lackorzynski:
Has energy surpassed timeliness? Scheduling energy-constrained mixed-criticality systems. 275-284
Embedded Systems and Applications
- Aaron Carroll, Gernot Heiser:
Unifying DVFS and offlining in mobile multicores. 287-296 - Yoshikazu Watanabe, Shuichi Karino, Yoshinori Saida, Gen Morita, Takahiro Iihoshi:
STCoS: Software-defined traffic control for smartphones. 297-308 - Claire Pagetti, David Saussié, Romain Gratia, Eric Noulard, Pierre Siron:
The ROSACE case study: From Simulink specification to multi/many-core execution. 309-318
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