Volume 1, Number 1/2, 2005

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  Yunsi Fei, Niraj K. Jha: Integrated functional partitioning and synthesis for low power distributed systems of systems-on-a-chip. 2-13
• 
  Prabhat Mishra, Nikil D. Dutt, Narayanan Krishnamurthy, Magdy S. Abadir: A methodology for validation of microprocessors using symbolic simulation. 14-22
• 
  Kai-Yuan Jan, Chih-Bin Fan, An-Chao Kuo, Wen-Chi Yen, Youn-Long Lin: A platform based SOC design methodology and its application in image compression. 23-32
• 
  Marek Jersak, Kai Richter, Rolf Ernst: Performance analysis for complex embedded applications. 33-49
• 
  Gabriella Kókai, Hans Holm Frühauf, Feng Xu: Adaptive smart antennae receiver controlled by a hardware-based genetic optimiser. 50-64
• 
  Christophe Bobda: CoreMap: a rapid prototyping environment for distributed reconfigurable systems. 65-77
• 
  Seppo Virtanen, Tero Nurmi, Jani Paakkulainen, Johan Lilius: A system-level framework for designing and evaluating protocol processor architectures. 78-90
• 
  Jingzhao Ou, Seonil B. Choi, Viktor K. Prasanna: Energy-efficient hardware/software co-synthesis for a class of applications on reconfigurable SoCs. 91-102
• 
  Iuliana Bacivarov, Aimen Bouchhima, Sungjoo Yoo, Ahmed Amine Jerraya: ChronoSym: a new approach for fast and accurate SoC cosimulation. 103-111
• 
  Nacer-Eddine Zergainoh, Amer Baghdadi, Ahmed Amine Jerraya: Hardware/software codesign of on-chip communication architecture for application-specific multiprocessor system-on-chip. 112-124
• 
  Tsung-Han Tsai, Chun-Nan Liu: A hardware/software co-design case study on MPEG AAC audio decoder. 125-133
• 
  Miroslav N. Velev, Randal E. Bryant: TLSim and EVC: a term-level symbolic simulator and an efficient decision procedure for the logic of equality with uninterpreted functions and memories. 134-149

Volume 1, Number 3/4, 2005

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  Sebastian Lange, Martin Middendorf: Multi task hyperreconfigurable architectures: models and reconfiguration problems. 154-164
• 
  Ali Ahmadinia, Christophe Bobda, Jürgen Teich: Online placement for dynamically reconfigurable devices. 165-178
• 
  Tyson S. Hall, Christopher M. Twigg, Paul E. Hasler, David V. Anderson: Developing large-scale field-programmable analog arrays for rapid prototyping. 179-192
• 
  Michael Ullmann, Michael Hübner, Jürgen Becker: On-demand FPGA run-time system for flexible and dynamical reconfiguration. 193-204
• 
  Eric J. Swankoski, Narayanan Vijaykrishnan, Richard R. Brooks, Mahmut T. Kandemir, Mary Jane Irwin: Symmetric encryption in reconfigurable and custom hardware. 205-217
• 
  Doris Ching, Patrick Schaumont, Ingrid Verbauwhede: Integrated modelling and generation of a reconfigurable network-on-chip. 218-227
• 
  Emanuele Lattanzi, Aman Gayasen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Luca Benini, Alessandro Bogliolo: Improving Java performance using dynamic method migration on FPGAs. 228-236
• 
  Nazar A. Saqib, Francisco Rodríguez-Henríquez, Arturo Díaz-Pérez: A reconfigurable processor for high speed point multiplication in elliptic curves. 237-249
• 
  Jing Huang, Mehdi Baradaran Tahoori, Fabrizio Lombardi: A probabilistic analysis of fault tolerance for switch block array in FPGAs. 250-262
• 
  Michael Hübner, Michael Ullmann, Jürgen Becker: Realtime configuration code decompression for dynamic FPGA self reconfiguration: evaluation and implementation. 263-273
• 
  Heiko Kalte, Boris Kettelhoit, Markus Köster, Mario Porrmann, Ulrich Rückert: A system approach for partially reconfigurable architectures. 274-290
• 
  Manish Handa, Ranga Vemuri: Hardware assisted two dimensional ultra fast online placement. 291-299

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