2. SLIP 2000: San Diego, CA, USA

@proceedings{DBLP:conf/slip/2000,
  title     = {The Second IEEE/ACM International Workshop on System-Level Interconnect
               Prediction (SLIP 2000), April 8-9, 2000, San Diego, California,
               Proceedings},
  booktitle = {SLIP},
  publisher = {ACM},
  year      = {2000},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

• Phillip Christie:
  Managing interconnect resources (tutorial). 1-51
  
• Denis Deschacht, Grégory Servel, Fabrice Huret, Erick Paleczny, Patrick Kennis:
  Theoretical limits for signal reflections due to inductance for on-chip interconnections. 55-60
  
• Mariagrazia Graziano, Marco Delaurenti, Maurizio Zamboni:
  Power supply design parameters prediction for high performance IC design flows. 61-67
  
• Imed Ben Dhaou, Hannu Tenhunen:
  Energy efficient high-speed on-chip signaling in deep-submicron CMOS technology. 69-76
  
• Dennis Sylvester:
  Measurement techniques and interconnect estimation. 79-81
  
• Krishna Saraswat, Shukri J. Souri, Kaustav Banerjee, Pawan Kapur:
  Performance analysis and technology of 3-D ICs. 85-90
  
• Srinivas Bodapati, Farid N. Najm:
  Pre-layout estimation of individual wire lengths. 93-98
  
• Dirk Stroobandt, Herwig Van Marck:
  Efficient representation of interconnection length distributions using generating polynomials. 99-105
  
• Payman Zarkesh-Ha, Jeffrey A. Davis, William Loh, James D. Meindl:
  Prediction of interconnect fan-out distribution using Rent's rule. 107-112
  
• Andrew B. Kahng, Dirk Stroobandt:
  Wiring layer assignments with consistent stage delays. 115-122
  
• James W. Joyner, Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl:
  Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architectures. 123-127
  
• Peng Li, Pranab K. Nag, Wojciech Maly:
  Cost based tradeoff analysis of standard cell designs. 129-135
  
• Louis Scheffer, Eric Nequist:
  Why interconnect prediction doesn't work. 139-144
  
• Jeffrey A. Davis, Raguraman Venkatesan, Keith A. Bowman, James D. Meindl:
  Gigascale integration (GSI) interconnect limits and n-tier multilevel interconnect architectural solutions (discussion session). 147-148
  
• Amir H. Farrahi:
  Estimation and removal or routing congestion (discussion session). 149
  

Last update Fri May 25 08:39:45 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page