5. SIES 2010: Trento, Italy

System Level

• Sandro Penolazzi, Ingo Sander, Ahmed Hemani:
  Inferring Energy and Performance Cost of RTOS in Priority-Driven Scheduling. 1-8
  
• Harald Voit, Reinhard Schneider, Dip Goswami, Anuradha Annaswamy, Samarjit Chakraborty:
  Optimizing Hierarchical Schedules for Improved Control Performance. 9-17
  
• Michal Sojka, Pavel Písa, Martin Petera, Ondrej Spinka, Zdenek Hanzálek:
  A Comparison of Linux CAN Drivers and their Applications. 18-27
  
• Christoph Kuznik, Gilles B. Defo, Wolfgang Müller:
  Verification of a CAN bus model in SystemC with functional coverage. 28-35
  

Networks

• Carlo Caione, Davide Brunelli, Luca Benini:
  Compressive sensing optimization over ZigBee networks. 36-44
  
• Orazio Mirabella, Lucia Lo Bello, Mario Collotta:
  An innovative frequency hopping management mechanism for Bluetooth-based industrial networks. 45-50
  
• Hsin-Chou Chi, Tat-Seng Chang, Chia-Ming Wu:
  Design of a Reconfigurable Pipelined Switch for Faulty On-Chip Networks. 51-56
  

Industrial Designs

• Luca Bochi Saldanha, Robert Hartmann, Christophe Bobda:
  Scratch Detector - A FPGA Based System for Scratch Detection in Industrial Picture Development. 57-62
  
• Alexander Smirnov, Kimmo Tolsa, Rafal Jastrzebski:
  Implementation of a bumpless switch in axial magnetic bearings. 63-68
  
• Koldo Basterretxea, Inés del Campo, Javier Echanobe:
  A semi-active suspension embedded controller in a FPGA. 69-78
  
• Kay Klobedanz, Gilles B. Defo, Wolfgang Müller, Timo Kerstan:
  Distributed Coordination of Task Migration for Fault-Tolerant FlexRay Networks. 79-87
  

Simulation and Methodology

• Mohammad Mostafizur Rahman Mozumdar, Luciano Lavagno, Laura Vanzago, Alberto L. Sangiovanni-Vincentelli:
  HILAC: A framework for Hardware In the Loop simulation and multi-platform Automatic Code Generation of WSN Applications. 88-97
  
• Charles André, Frédéric Mallet, Julien DeAntoni:
  VHDL Observers for Clock Constraint Checking. 98-107
  
• Borzoo Bonakdarpour, Marius Bozga, Mohamad Jaber, Jean Quilbeuf, Joseph Sifakis:
  Automated Conflict-free distributed implementation of component-based models. 108-117
  
• Dominique Gückel, Jörg Brauer, Stefan Kowalewski:
  A system for synthesizing abstraction-enabled simulators for binary code verification. 118-127
  

Real-Time

• Mathieu Jan, Vincent David, Jimmy Lalande, Maurice Pitel:
  Usage of the safety-oriented real-time OASIS approach to build deterministic protection relays. 128-135
  
• Tommaso Cucinotta, Dario Faggioli:
  An Exception Based Approach to Timing Constraints Violations in Real-Time and Multimedia Applications. 136-145
  
• Kristina Kunert, Elisabeth Uhlemann, Magnus Jonsson:
  Enhancing Reliability in IEEE 802.11 Based Real-Time Networks through Transport Layer Retransmissions. 146-155
  

Wireless Networks

• Gianluca Franchino, Giorgio C. Buttazzo, Mauro Marinoni:
  An Energy-Aware Algorithm for TDMA MAC Protocols in Real-Time Wireless Networks. 156-165
  
• David Macii, Anton Ageev, Luca Abeni:
  An Energy Saving Criterion for Wireless Sensor Networks with Time Synchronization Requirements. 166-173
  
• Luca Santinelli, Mangesh Chitnis, Christian Nastasi, Fabio Checconi, Giuseppe Lipari, Paolo Pagano:
  A Component-Based Architecture for Adaptive Bandwidth Allocation in Wireless Sensor Networks. 174-183
  

Work-in-Progress

• Khaled Rahmouni, Frédéric Pétrot:
  Improving the tests coverage of a medium voltage protection device using system simulation approaches. 184-187
  
• Chuzo Ninagawa, Tomotaka Sato, Tomohisa Yamada:
  Multi-Server Web Industrial Facility Monitoring by Only COTS Browser's Existing Functionality. 188-191
  
• Maria Isabel de la Fuente, Javier Echanobe, Inés del Campo, Loreto Susperregui, Iñaki Maurtua:
  Development of an Embedded System for Visual Servoing in an Industrial Scenario. 192-196
  
• Xavier Dumas, Frédéric Boniol, Philippe Dhaussy, Eric Bonnafous:
  Context Modelling and Partial-Order Reduction: Application to SDL Industrial Embedded Systems. 197-200
  
• Gunnar Prytz, Jonny Skaalvik:
  Redundant and synchronized EtherCAT network. 201-204
  
• Klaus Schmidt, Ece Guran Schmidt:
  A Longest-Path Problem for Evaluating the Worst-Case Packet Delay of Switched Ethernet. 205-208
  
• Ece Guran Schmidt, Melih Alkan, Klaus Schmidt, Emrah Yuruklu, Utku Karakaya:
  Performance Evaluation of FlexRay/CAN Networks Interconnected by a Gateway. 209-212
  
• Swaytha Sasidharan, Fernando Pianegiani, David Macii:
  A Protocol Performance Comparison in Modular WSNs for Data Center Server Monitoring. 213-216
  
• Vassiliki Sfyrla, Georgios Tsiligiannis, Iris Safaka, Marius Bozga, Joseph Sifakis:
  Compositional Translation of Simulink Models into Synchronous BIP. 217-220
  
• Kunjesh Shah, Tiberiu Seceleanu, Mikael Gidlund:
  Design and Implementation of a WirelessHART Simulator for Process Control. 221-224
  
• Sara Real, Hector Posadas, Eugenio Villar:
  L2 Cache Modeling based on address modification for Native Co-Simulation in SystemC. 225-228
  
• Vincent Lefftz, Jean Bertrand, Hugues Cassé, Christophe Clienti, Philippe Coussy, Laurent Maillet-Contoz, Philippe Mercier, Pierre Moreau, Laurence Pierre, Emmanuel Vaumorin:
  A Design Flow for Critical Embedded Systems. 229-233
  
• Julian Viejo, Jose Ignacio Villar, Jorge Juan, Alejandro Millán, Manuel Jesús Bellido Díaz, Enrique Ostúa:
  Design and implementation of a suitable core for on-chip long-term verification. 234-237
  

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