Architectures I

• 
  Takashi Miyamori, Kunle Olukotun: A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications. 2-11
• 
  Csaba Andras Moritz, Donald Yeung, Anant Agarwal: Exploring Optimal Cost-Performance Designs for Raw Microprocessors. 12-27
• 
  Charlé R. Rupp, Mark Landguth, Tim Garverick, Edson Gomersall, Harry Holt, Jeffrey M. Arnold, Maya Gokhale: The NAPA Adaptive Processing Architecture. 28-

Special Purpose Systems

• 
  Steven Swanchara, Scott J. Harper, Peter M. Athanas: A Stream-Based Configurable Computing Radio Testbed. 40-47
• 
  Apostolos Dollas, Euripides Sotiriades, Apostolos Emmanouelides: Architecture and Design of GE1, a FCCM for Golomb Ruler Derivation. 48-

Architectures II

• 
  Akihisa Ohta, Tsuyoshi Isshiki, Hiroaki Kunieda: New FPGA Architecture for Bit-Serial Pipeline Datapath. 58-67
• 
  Kouichi Nagami, Kiyoshi Oguri, Tsunemichi Shiozawa, Hideyuki Ito, Ryusuke Konishi: Plastic Cell Architecture: Towards Reconfigurable Computing for General-Purpose. 68-77
• 
  Stephen M. Scalera, Jóse R. Vázquez: The Design and Implementation of a Context Switching FPGA. 78-

Applications I

• 
  Rhett D. Hudson, David I. Lehn, Peter M. Athanas: A Run-Time Reconfigurable Engine for Image Interpolation. 88-95
• 
  Mark Shand, Laurent Moll: Hardware/Software Integration in Solar Polarimetry. 96-

Compilers

• 
  Andrew A. Duncan, David C. Hendry, Peter Gray: An Overview of the COBRA-ABS High Level Synthesis System for Multi-FPGA Systems. 106-115
• 
  Darren C. Cronquist, Paul Franklin, Stefan G. Berg, Carl Ebeling: Specifying and Compiling Applications for RaPiD. 116-125
• 
  Maya Gokhale, Janice M. Stone: NAPA C: Compiling for a Hybrid RISC/FPGA Architecture. 126-

Tools for Run Time Reconfiguration

• 
  Scott Hauck, Zhiyuan Li, Eric J. Schwabe: Configuration Compression for the Xilinx XC6200 FPGA. 138-146
• 
  Nabeel Shirazi, Wayne Luk, Peter Y. K. Cheung: Automating Production of Run-Time Reconfigurable Designs. 147-

Module Generation

• 
  Michael Chu, Nicholas Weaver, Kolja Sulimma, André DeHon, John Wawrzynek: Object Oriented Circuit-Generators in Java. 158-166
• 
  Oskar Mencer, Martin Morf, Michael J. Flynn: PAM-Blox: High Performance FPGA Design for Adaptive Computing. 167-174
• 
  Peter Bellows, Brad L. Hutchings: JHDL - An HDL for Reconfigurable Systems. 175-

Applications II

• 
  Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik: Accelerating Boolean Satisfiability with Configurable Hardware. 186-195
• 
  Azra Rashid, Jason Leonard, William H. Mangione-Smith: Dynamic Circuit Generation for Solving Specific Problem Instances of Boolean Satisfiability. 196-

Arithmetic

• 
  Walter B. Ligon III, Scott McMillan, Greg Monn, Kevin Schoonover, Fred Stivers, Keith D. Underwood: A Re-evaluation of the Practicality of Floating-Point Operations on FPGAs. 206-215
• 
  Alexandre F. Tenca, Milos D. Ercegovac: A Variable Long-Precision Arithmetic Unit Design for Reconfigurable Coprocessor Architectures. 216-225
• 
  Simon D. Haynes, Peter Y. K. Cheung: A Reconfigurable Multiplier Array For Video Image Processing Tasks, Suitable For Embedding In An FPGA Structure. 226-

Applications III

• 
  Satnam Singh, Robert Slous: Accelerating Adobe Photoshop with the Reconfigurable Logic. 236-244
• 
  Karlheinz Weiß, Ronny Kistner, Arno Kunzmann, Wolfgang Rosenstiel: Analysis of the XC6000 Architecture for Embedded System Design. 245-

Poster Session 1

• 
  Philip Heng Wai Leong, P. K. Tsang, T. K. Lee: A FPGA Based Forth Microprocessor. 254-255
• 
  Tsuyoshi Hamada, Toshiyuki Fukushige, Atsushi Kawai, Junichiro Makino: PROGRAPE-1: A Programmable Special-Purpose Computer for Many-Body Simulations. 256-257
• 
  José Carlos Alves, José Silva Matos: RVC - A Reconfigurable Coprocessor for Vector Processing Applications. 258-259
• 
  I. M. Bland, Graham M. Megson: The Systolic Array Genetic Algorithm, An Example of Systolic Arrays as a Reconfigurable Design Methodology. 260-261
• 
  Andreas Kugel, Klaus Kornmesser, R. Lay, J. Ludvig, Reinhard Männer, K. H. Noffz, Stephan Rühl, M. Sessler, Harald Simmler, Holger Singpiel: 50 kHz Pattern Recognition on the Large FPGA Processor Enable++. 262-
• 
  Masato Motomura, Yoshiharu Aimoto, Atsufkni Shibayama, Yoshikazu Yabe, Masakazu Yamashina: An Embedded DRAM-FPGA Chip with Instantaneous Logic Reconfiguration. 264-266
• 
  Jeffrey M. Arnold: Mapping the MD5 Hash Algorithm onto the NAPA Architecture. 267-268
• 
  Apostolos Dollas, Euripides Sotiriades, Apostolos Emmanouelides, Lee House: General Purpose vs. Custom FCCM's: a Comparison of Splash2, Quickturn RPM, and GE1 for Golomb Ruler Derivation. 269-270
• 
  Jeffrey M. Arnold: An Architecture Simulator for National Semiconductor's Adaptive Processing Architecture (NAPA). 271-272
• 
  S. Kumar, Luiz Pires, D. Pandalai, M. Vojta, J. Golusky, S. Wadi, Henk A. E. Spaanenburg: Benchmarking Technology for Configurable Computing System. 273-274
• 
  M. F. Sakr, Steven P. Levitan, C. Lee Giles, Donald M. Chiarulli: Reconfigurable Processor Architectures Exploiting High Bandwidth Optical Channels. 275-

Poster Session 2

• 
  André Stauffer, Moshe Sipper, Andrés Pérez-Uribe: Some Applications of FPGAs in Bio-Inspired Hardware. 278-279
• 
  João Canas Ferreira, José Silva Matos: A Prototype System for Rapid Application Development using Dynamically Reconfigurable Hardware. 280-281
• 
  Ruth Sivilotti, Young Cho, Wen-King Su, Danny Cohen, Brian Bray: Scalable Network Based FPGA Accelerators for an Automatic Target Recognition Application. 282-283
• 
  T. K. Lee, Philip Heng Wai Leong, K. H. Lee, K. T. Chan, S. K. Hui, H. K. Yeung, M. F. Lo, J. H. M. Lee: An FPGA Implementation of GENET for Solving Graph Coloring Problems . 284-285
• 
  Stephen P. Crago, Brian Schott, Robert Parker: SLAAC: A Distributed Architecture for Adaptive Computing. 286-287
• 
  Jacques-Olivier Haenni, Jean-Luc Beuchat, Eduardo Sanchez: RENCO: A Reconfigurable Network Computer. 288-289
• 
  Emeka Mosanya, Jean-Michel Puiatti, Eduardo Sanchez: Hardware Implementation of Generalized Profile Search on the GENSTORM Machine. 290-291
• 
  Hagen Ploog, Dirk Timmermann: FPGA-Based Architecture Evaluation of Cryptographic Coprocessors for Smartcards. 292-293
• 
  Matthew Moe, Herman Schmit, Seth Copen Goldstein: Characterization and Parameterization of a Pipeline Reconfigurable FPGA. 294-

Poster Session 3

• 
  Donald L. Hung, Jun Wang: A FPGA-Based Custom Computing System for Solving the Assignment Problem. 298-299
• 
  Gordon J. Brebner: Circlets: Circuits as Applets. 300-301
• 
  Jack S. N. Jean, Karen A. Tomko, Vikram Yavagal, Robert Cook, Jignesh Shah: Dynamic Reconfiguration to Support Concurrent Applications. 302-303
• 
  Pascal Poiré, Marc-André Cantin, Hervé Daniel, Yves Blaquière, Yvon Savaria: A Comparative Analysis of Fuzzy ART Neural Network Implementations: The Advantages of Reconfigurable Computing. 304-305
• 
  Paul S. Graham, Brent E. Nelson: Frequency-Domain Sonar Processing in FPGAs and DSPs. 306-307
• 
  Nicholas McKay, Thomas F. Melham, Kong Woei Susanto, Satnam Singh: Dynamic Specialization of XC6200 FPGAs by Partial Evaluation. 308-309
• 
  Tom Kean, Ann Duncan: DES Key Breaking, Encryption and Decryption on the XC6216. 310-311
• 
  Sriram Govindarajan, Iyad Ouaiss, Meenakshi Kaul, Vinoo Srinivasan, Ranga Vemuri: An Effective Design System for Dynamically Reconfigurable Architectures. 312-313
• 
  Andreas Dandalis, Viktor K. Prasanna: Mapping Homogeneous Computations onto Dynamically Configurable Coarse-Grained Architectures. 314-

Poster Session 4

• 
  Sakir Sezer, Roger Woods, Jean-Paul Heron, Alan J. Marshall: Fast Partial Reconfiguration for FCCMs. 318-319
• 
  Gunter Haug, Wolfgang Rosenstiel: Reconfigurable Hardware as Shared Resource for Parallel Threads. 320-321
• 
  Hanho Lee, Gerald E. Sobelman: Digit-Serial DSP Library for Optimized FPGA Configuration. 322-323
• 
  Pedro Merino, Margarida F. Jacome, Juan Carlos López: A Methodology for Task Based Partitioning and Scheduling of Dynamically Reconfigurable Systems. 324-325
• 
  Goran Doncev, Miriam Leeser, Shantanu Tarafdar: High Level Synthesis for Designing Custom Computing Hardware. 326-328
• 
  Karthikeya M. Gajjala Purna, Dinesh Bhatia: Temporal Partitioning and Scheduling for Reconfigurable Computing. 329-330
• 
  Luiz Maltar, Felipe M. G. França, Vladimir Castro Alves, Cláudio L. Amorim: Implementation of RNS Addition and RNS Multiplication into FPGAs. 331-332
• 
  Al Walters, Peter Athanas: A Scalable FIR Filter Using 32-bit Floating-Point Complex Arithmetic on a Configurable Computing Machine. 333-334
• 
  Nikhil D. Gupta, John K. Antonio, Jack M. West: Reconfigurable Computing for Space-Time Adaptive Processing. 335-336
• 
  Manoucher Shaditalab, Guy Bois, Mohamad Sawan: Self Sorting Radix_2 FFT on FPGA using Parallel Pipelined Distributed Arithmetic Blocks. 337-338
• 
  Donald Soderman, Yuri Panchul: Implementing C Algorithms in Reconfigurable Hardware Using C2Verilog. 339-

last updated on Sat May 18 04:53:48 2013 by the dblp team
data released under the ODC-BY 1.0 license
see also our legal information page