DSD 2005: Porto, Portugal

Cover

• Title Page.
  
• Copyright.
  

Introduction

• Message from the Program Chair.
  
• Conference Committees.
  

Keynote Speeches

• Melvin A. Breuer:
  Multi-media Applications and Imprecise Computation. 2-7
  
• Dirk Timmermann:
  Wireless Sensor Systems - Constraints and Opportunities. 8
  

SS2: Dependability and Testing of Digital Systems, Part 1. (S1)

• Milos Krstic, Eckhard Grass:
  BIST Technique for GALS Systems. 10-16
  
• Tun Li, Yang Guo, GongJie Liu, Sikun Li:
  Functional Vectors Generation for RT-Level Verilog Descriptions Based on Path Enumeration and Constraint Logic Programming. 17-25
  

System Synthesis, Part 1. Power and Component Driven System Synthesis (S2)

• Arnaud Cuccuru, Robert de Simone, Thierry Saunier, Günther Siegel, Yves Sorel:
  P2I: An Innovative MDA Methodology for Embedded Real-Time System. 26-33
  
• Dong Wu, Bashir M. Al-Hashimi, Marcus T. Schmitz, Petru Eles:
  Power-Composition Profile Driven Co-Synthesis with Power Management Selection for Dynamic and Leakage Energy Reduction. 34-41
  

Circuits Synthesis, Part 1. Arithmetic (S3)

• Andreas Lindahl, Lars Bengtsson:
  A Low-Power FIR Filter Using Combined Residue and Radix-2 Signed-Digit Representation. 42-47
  
• Mark G. Arnold:
  Approximating Trigonometric Functions with the Laws of Sines and Cosines using the Logarithmic Number System. 48-55
  

SS2: Dependability and Testing of Digital Systems, Part 2. (S4)

• Peter Filter, Hana Kubatova:
  Improvement of the Fault Coverage of the Pseudo-Random Phase in Column-Matching BIST. 56-63
  
• Lucía Costas, Juan J. Rodríguez-Andina:
  Characterization of Wavelet-Based Image Coding Systems for Algorithmic Fault Detection. 64-71
  
• Jaan Raik, Peeter Ellervee, Valentin Tihhomirov, Raimund Ubar:
  Improved Fault Emulation for Synchronous Sequential Circuits. 72-78
  
• Joachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold A. Pleskacz:
  Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. 79-82
  
• Zhiyuan He, Gert Jervan, Zebo Peng, Petru Eles:
  Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment. 83-87
  

System Synthesis, Part 2. Component Based System Synthesis (S5)

• Nabil Abdelli, Pierre Bomel, Emmanuel Casseau, Anne-Marie Fouilliart, Christophe Jégo, Philippe Kajfasz, Bertrand Le Gal, Nathalie Le Heno:
  Hardware Virtual Components Compliant with Communication System Standards. 88-95
  
• Pierre Bomel, Nabil Abdelli, Eric Martin, Anne-Marie Fouilliart, Emmanuel Boutillon, Philippe Kajfasz:
  High-Level Synthesis in Latency Insensitive System Methodology. 96-101
  
• Tero Vallius, Juha Röning:
  Embedded Object Architecture. 102-107
  
• Soujanna Sarkar, Subash G. Chandar:
  An Effective Framework for Enabling the Reuse of External Soft IP. 108-113
  

Circuits Synthesis, Part 2. Logic Synthesis (S6)

• Dariusz Kania, Józef Kulisz, Adam Milik:
  A Novel Method of Two-Stage Decomposition Dedicated for PAL-based CPLDs. 114-121
  
• Md. Sumon Shahriar, A. R. Mustafa, Chowdhury Farhan Ahmed, Abu Ahmed Ferdaus, A. N. M. Zaheduzzaman, Shahed Anwar, Hafiz Md. Hasan Babu:
  An Advanced Minimization Technique for Multiple Valued Multiple Output Logic Expressions Using LUT and Realization Using Current Mode CMOS. 122-126
  
• Robert Czerwinski, Dariusz Kania:
  State Assignment for PAL-based CPLDs. 127-134
  
• Vladimir Ciric, Ivan Milentijevic:
  Coefficient Bit Reordering Method for Configurable FIR Filtering on Folded Bit-plane Array. 135-138
  
• Krzysztof S. Berezowski, Sarma B. K. Vrudhula:
  Automatic Design of Binary and Multiple-Valued Logic Gates on RTD Series. 139-143
  

SS1: Wireless Sensor Systems, Part 1. (S7)

• Panu Hämäläinen, Jari Heikkinen, Marko Hännikäinen, Timo D. Hämäläinen:
  Design of Transport Triggered Architecture Processors for Wireless Encryption. 144-152
  
• C. Siu, Soraya Kasnavi, Kris Iniewski, F. Nabki:
  RF CMOS Circuits for Ad-Hoc Networks and Wearable Computing. 153-160
  
• Petri Kukkala, Marko Hännikäinen, Timo D. Hämäläinen:
  Co-simulation of Wireless Local Area Network Terminals with Protocol Software Implemented in SDL. 161-164
  
• Senthil Jayapal, S. Ramachandran, R. Bhutada, Yiannos Manoli:
  Optimization of Electronic Power Consumption in Wireless Sensor Nodes. 165-169
  
• Danielly Cruz, Edna Barros:
  Vital Signs Remote Management System for PDAs. 170-175
  

Verification Techniques, Part 1. (S8)

• Tun Li, Dan Zhu, Yang Guo, GongJie Liu, Sikun Li:
  MA2TG: A Functional Test Program Generator for Microprocessor Verification. 176-183
  
• Francisco Duarte, José Machado da Silva, José Carlos Alves, G. A. Pinho, José Silva Matos:
  A processor for testing mixed-signal cores in System-on-Chip. 184-191
  
• Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas:
  Functional Test Generation Remote Tool. 192-195
  
• Daniel Karlsson, Petru Eles, Zebo Peng:
  Validation of Embedded Systems Using Formal Method Aided Simulation. 196-201
  

Application Specific Architectures, Part 1. (S9)

• Massimo Rovini, Nicola E. L'Insalata, Francesco Rossi, Luca Fanucci:
  VLSI Design of a High-Throughput Multi-Rate Decoder for Structured LDPC Codes. 202-209
  
• Luciano Volcan Agostini, Roger Endrigo Carvalho Porto, Sergio Bampi, Ivan Saraiva Silva:
  A FPGA Based Design of a Multiplierless and Fully Pipelined JPEG Compressor. 210-213
  
• Jin Hwan Park:
  Reconfigurable Parallel Approximate String Matching on FPGAs. 214-217
  
• Salvatore Vitabile, Vincenzo Conti, Fulvio Gennaro, Filippo Sorbello:
  Efficient MLP Digital Implementation on FPGA. 218-222
  
• Michael Freeman, Jim Austin:
  Designing a Binary Neural Network Co-processor. 223-227
  
• Hamid Safizadeh, Hamid Noori, Mehdi Sedighi, Ali Jahanian, Neda Zolfaghari:
  Efficient Host-Independent Coprocessor Architecture for Speech Coding Algorithms. 227-230
  
• Nadia Nedjah, Luiza de Macedo Mourelle:
  Massively Parallel Hardware Architecture for Genetic Algorithms. 231-234
  
• Oswaldo Cadenas, Graham M. Megson, Daniel Jones:
  Implementation of a block based neural branch predictor. 235-238
  
• Stanley Hyduke, Vladimir Hahanov, Volodymyr Obrizan, Olesya Guz:
  PRUS - Processor Network for Digital Circuit Implementation. 239-242
  
• Seppo Virtanen, Jani Paakkulainen, Tero Nurmi:
  Capturing Processor Architectures from Protocol Processing Applications: a Case Study. 243-246
  
• Zhaojun Wo, Israel Koren, Maciej J. Ciesielski:
  Yield-aware Floorplanning. 247-253
  

SS1: Wireless Sensor Systems, Part 2. (S10)

• Kashif Virk, Jan Madsen, Andreas Vad Lorentzen, Martin Leopold, Philippe Bonnet:
  Design of A Development Platform for HW/SW Codesign ofWireless Integrated Sensor Nodes. 254-260
  
• Y. Ghiassi, Mohammad M. M. Rad, Mohammad S. Nikjoo, Ali Hesam Mohseni, Babak Hossein Khalaj:
  An Efficient MAC Protocol for Sensor Network Considering Energy Consumption and Information Retrieval Pattern. 261-266
  
• Mikko Kohvakka, Marko Hännikäinen, Timo D. Hämäläinen:
  Wireless Sensor Network Implementation for Industrial Linear Position Metering. 267-275
  

Verification Techniques, Part 2. (S11)

• Mária Fischerová, Martin Simlastík:
  MemBIST Applet for Learning Principles of Memory Testing and Generating Memory BIST. 276-281
  
• Miguel Pereira, Enrique Soto, Juan J. Rodríguez-Andina, Francisco J. González-Castaño:
  High-Level Modelling and Detection of the Faulty Behaviour of VOQ Switches under Balanced Traffic. 282-288
  
• Piotr Patronik:
  Delay Testability Properties of Circuits Implementing Threshold and Symmetric Functions. 289-297
  

Application Specific Architectures, Part 2. (S12)

• Roberto R. Osorio, Javier D. Bruguera:
  A New Architecture for fast Arithmetic Coding in H.264 Advanced Video Coder. 298-305
  
• Pedro Trancoso, Maria Charalambous:
  Exploring Graphics Processor Performance for General Purpose Applications. 306-313
  
• Kenneth B. Kent, Sharon Van Schaick, Jacqueline E. Rice, Patricia A. Evans:
  Hardware-Based Implementation of the Common Approximate Substring Algorithm. 314-321
  

System Synthesis, Part 3. High Level Language based System Synthesis (S13)

• Sergio Saponara, Michele Cassiano, Stefano Marsi, Riccardo Coen, Luca Fanucci:
  Cost-effective VLSI Design of Non Linear Image Processing Filters. 322-329
  
• Per Andersson, Krzysztof Kuchcinski:
  Java to Hardware Compilation for non Data Flow Applications. 330-337
  
• Ka L. Man:
  Formal Communication Semantics of SystemC^FL. 338-345
  
• Sérgio Martins, José Carlos Alves:
  A high-level tool for the design of custom image processing systems. 346-349
  
• Nikolay Kavaldjiev, Gerard J. M. Smit, Pierre G. Jansen:
  Throughput of Streaming Applications Running on a Multiprocessor Architecture. 350-355
  

Reconfigurable Systems, Part 1. (S14)

• Christophe Wolinski, Krzysztof Kuchcinski:
  A Constraints Programming Approach for Fabric Cell Synthesis. 356-363
  
• Yang Qu, Kari Tiensyrjä, Juha-Pekka Soininen:
  SystemC-based Design Methodology for Reconfigurable System-on-Chip. 364-371
  
• Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi:
  Reducing Inter-Configuration Memory Usage and Performance Improvement in Reconfigurable Computing Systems. 372-378
  
• Ghaffari Fakhreddine, Michel Auguin, Mohamed Abid, Benjemaa Maher:
  An Adaptive On-Line HW/SW Partitioning for Soft Real Time Reconfigurable Systems. 379-382
  
• Miguel Lino Silva, João Canas Ferreira:
  Using a Tightly-Coupled Pipeline in Dynamically Reconfigurable Platform FPGAs. 383-387
  

Data Management in SoC, Part 1. (S15)

• Sander Stuijk, Twan Basten, Bart Mesman, Marc Geilen:
  Predictable embedding of large data structures in multiprocessor networks-on-chip. 388-396
  
• Fredy Rivera, Milagros Fernández, Nader Bagherzadeh:
  An Approach to Execute Conditional Branches onto SIMD Multi-Context Reconfigurable Architectures. 396-402
  
• Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng:
  Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip. 403-411
  

SS3: Remonte Educational Tools for Design and Testing, Part 1 (S16)

• Artur Jutman, Jaan Raik, Raimund Ubar, V. Vislogubov:
  An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform. 412-419
  
• Josef Strnadel, Zdenek Kotásek:
  Educational Tool for the Demonstration of DfT Principles Based on Scan Methodologies. 420-427
  
• Oystein Gjermundnes, Einar J. Aas:
  Remote Path Delay Fault Simulation. 428-434
  
• Vladislav Nelayev, Viktor Stempitsky, Kirill A. Kudin:
  Internet-Based IC Technology Design and Simulation. 435-441
  

Circuits Synthesis, Part 3. Advanced Logic Synthesis (S17)

• Dariusz Kania, Adam Milik, Józef Kulisz:
  Decomposition of Multi-Output Functions for CPLDs. 442-449
  
• Lech Józwiak, Szymon Bieganski:
  High-quality Sub-function Construction in the Information-driven Circuit Synthesis with Gates. 450-459
  
• Mariusz Rawski, Pawel Tomaszewicz, Henry Selvaraj, Tadeusz Luba:
  Efficient Implementation of Digital Filters with Use of Advanced Synthesis Methods Targeted FPGA Architectures. 460-466
  
• Tsutomu Sasao, Yukihiro Iguchi, Takahiro Suzuki:
  On LUT Cascade Realizations of FIR Filters. 467-475
  

Performance Optimization: Architecture and Tools, Part 1. (S18)

• Pedro Trancoso:
  Dynamic Split: Flexible Border Between Instruction and Data Cache. 476-483
  
• Arnaldo Oliveira, Valery Sklyarov, António de Brito Ferrari:
  ARPA - A Technology Independent and Synthetizable System-on-Chip Model for Real-Time Applications. 484-491
  
• Danilo Pani, Giuseppe Passino, Luigi Raffo:
  Run-time Adaptive Resources Allocation and Balancing on Nanoprocessors Arrays. 492-499
  

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