CODES+ISSS 2010: Scottsdale, AZ, USA

Keynote talk

• Vida Ilderem:
  Embedded market: challenges and opportunities. 1-2
  

Application-specific algorithms and architectures

• B. V. N. Silpa, Gummidipudi Krishnaiah, Preeti Ranjan Panda:
  Rank based dynamic voltage and frequency scaling fortiled graphics processors. 3-12
  
• James Coole, Greg Stitt:
  Intermediate fabrics: virtual architectures for circuit portability and fast placement and routing. 13-22
  
• Ping Chao, Youn-Long Lin:
  An elastic software cache with fast prefetching for motion compensation in video decoding. 23-32
  

Reconfigurable and real-time system

• Felix Madlener, Julia Weingart, Sorin A. Huss:
  Verification of dynamically reconfigurable embedded systems by model transformation rules. 33-40
  
• Adrian Alin Lifa, Petru Eles, Zebo Peng, Viacheslav Izosimov:
  Hardware/software optimization of error detection implementation for real-time embedded systems. 41-50
  
• Martin Kero, Simon Aittamaa:
  Scheduling garbage collection in real-time systems. 51-60
  

Special session

• Tor E. Jeremiassen, Tim Kogel, Andrés Takach, Grant Martin, Adam Donlin, Karamvir Chatha:
  From ESL 2010 to ESL 2015. 61-62
  
• Xiaobo Sharon Hu, Richard C. Murphy, Sudip S. Dosanjh, Kunle Olukotun, Stephen Poole:
  Hardware/software co-design for high performance computing: challenges and opportunities. 63-64
  

Optimising multiprocessor and NoC platforms for performance, QoS, and reliability

• Jaume Joven, Andrea Marongiu, Federico Angiolini, Luca Benini, Giovanni De Micheli:
  Exploring programming model-driven QoS support for NoC-based platforms. 65-74
  
• Haris Javaid, Xin He, Aleksandar Ignjatovic, Sri Parameswaran:
  Optimal synthesis of latency and throughput constrained pipelined MPSoCs targeting streaming applications. 75-84
  
• Sudeep Pasricha, Yong Zou, Dan Connors, Howard Jay Siegel:
  OE+IOE: a novel turn model based fault tolerant routing scheme for networks-on-chip. 85-94
  

Power-aware design

• Cheng-Yen Lin, Po-Yu Chen, Chun-Kai Tseng, Chung-Wen Huang, Chia-Chieh Weng, Chi-Bang Kuan, Shih-Han Lin, Shi-Yu Huang, Jenq Kuen Lee:
  Power aware SID-based simulator for embedded multicore DSP subsystems. 95-104
  
• Lide Zhang, Birjodh Tiwana, Zhiyun Qian, Zhaoguang Wang, Robert P. Dick, Zhuoqing Morley Mao, Lei Yang:
  Accurate online power estimation and automatic battery behavior based power model generation for smartphones. 105-114
  
• Concepción Sanz Pineda, Manuel Prieto, José Ignacio Gómez, Christian Tenllado, Francky Catthoor:
  Statistical approach in a system level methodology to deal with process variation. 115-124
  

MPSoC: analysis and synthesis

• Marc Geilen, Sander Stuijk:
  Worst-case performance analysis of synchronous dataflow scenarios. 125-134
  
• Felix Reimann, Michael Glaß, Christian Haubelt, Michael Eberl, Jürgen Teich:
  Improving platform-based system synthesis by satisfiability modulo theories solving. 135-144
  
• Adam S. Hartman, Donald E. Thomas, Brett H. Meyer:
  A case for lifetime-aware task mapping in embedded chip multiprocessors. 145-154
  

Memory and communication architecture

• Yosi Ben-Asher, Nadav Rotem:
  Automatic memory partitioning: increasing memory parallelism via data structure partitioning. 155-162
  
• Kim Grüttner, Henning Kleen, Frank Oppenheimer, Achim Rettberg, Wolfgang Nebel:
  Towards a synthesis semantics for systemC channels. 163-172
  
• Zhiwei Qin, Yi Wang, Duo Liu, Zili Shao:
  Demand-based block-level address mapping in large-scale NAND flash storage systems. 173-182
  

Embedded tutorial

• Philippe Coussy, Andrés Takach, Michael McNamara, Mike Meredith:
  An introduction to the SystemC synthesis subset standard. 183-184
  
• Tom Vander Aa, Praveen Raghavan, Scott A. Mahlke, Bjorn De Sutter, Aviral Shrivastava, Frank Hannig:
  Compilation techniques for CGRAs: exploring all parallelization approaches. 185-186
  

Memory architecture for embedded systems

• Garo Bournoutian, Alex Orailoglu:
  Dynamic, non-linear cache architecture for power-sensitive mobile processors. 187-194
  
• Hassan Ghasemzadeh, Roozbeh Jafari:
  A greedy buffer allocation algorithm for power-aware communication in body sensor networks. 195-204
  
• Kwangyoon Lee, Alex Orailoglu:
  High durability in NAND flash memory through effective page reuse mechanisms. 205-212
  

New design approaches for network-on-chip systems

• Glenn Leary, Karam S. Chatha:
  A holistic approach to network-on-chip synthesis. 213-222
  
• Thomas Ebi, Mohammad Abdullah Al Faruque, Jörg Henkel:
  NeuroNoC: neural network inspired runtime adaptation for an on-chip communication architecture. 223-230
  
• Paul Bogdan, Radu Marculescu:
  Workload characterization and its impact on multicore platform design. 231-240
  

Novel techniques for accelerating system simulation

• Christoph Schumacher, Rainer Leupers, Dietmar Petras, Andreas Hoffmann:
  parSC: synchronous parallel systemc simulation on multi-core host architectures. 241-246
  
• Gummidipudi Krishnaiah, B. V. N. Silpa, Preeti Ranjan Panda, Anshul Kumar:
  FastFwd: an efficient hardware acceleration technique for trace-driven network-on-chip simulation. 247-256
  
• Hao Li, Dong Tong, Kan Huang, Xu Cheng:
  FEMU: a firmware-based emulation framework for SoC verification. 257-266
  

Embedded software performance optimization

• Daniel Cordes, Peter Marwedel, Arindam Mallik:
  Automatic parallelization of embedded software using hierarchical task graphs and integer linear programming. 267-276
  
• Marco Lattuada, Fabrizio Ferrandi:
  Performance modeling of embedded applications with zero architectural knowledge. 277-286
  
• Michael A. Baker, Amrit Panda, Nikhil Ghadge, Aniruddha Kadne, Karam S. Chatha:
  A performance model and code overlay generator for scratchpad enhanced embedded processors. 287-296
  

Reliability and memory issues in MPSoCs

• Xiang Yun, Thidapat Chantem, Robert P. Dick, Xiaobo Sharon Hu, Li Shang:
  System-level reliability modeling for MPSoCs. 297-306
  
• Chanhee Lee, Hokeun Kim, Hae-woo Park, Sungchan Kim, Hyunok Oh, Soonhoi Ha:
  A task remapping technique for reliable multi-core embedded systems. 307-316
  
• Ke Bai, Aviral Shrivastava:
  Heap data management for limited local memory (LLM) multi-core processors. 317-326
  

Special session

• Radu Marculescu, Christof Teuscher, Partha Pratim Pande:
  Unconventional fabrics, architectures, and models for future multi-core systems. 327-328
  

Tutorials

• Maarten Wiggers, Lothar Thiele, Edward A. Lee, Simon Schliecker, Marco Bekooij:
  Modeling and analyzing real-time multiprocessor systems. 329-330
  
• Christopher X. Brooks, Edward A. Lee, Stavros Tripakis:
  Exploring models of computation with ptolemy II. 331-332
  

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