CODES 2001: Copenhagen, Denmark

• Wayne Wolf:
  CODES and co-design: a look back and a look forward. 2
  
• Axel Jantsch, Ingo Sander, Wenbiao Wu:
  The usage of stochastic processes in embedded system specifications. 5-10
  
• Neal K. Tibrewala, JoAnn M. Paul, Donald E. Thomas:
  Modeling and evaluation of hardware/software designs. 11-16
  
• Alessandro Fin, Franco Fummi, Maurizio Martignano, Mirko Signoretto:
  SystemC: a homogenous environment to test embedded systems. 17-22
  
• Grant Martin, Luciano Lavagno, Jean Louis-Guerin:
  Embedded UML: a merger of real-time UML and co-design. 23-28
  
• Geert Vanmeerbeeck, Patrick Schaumont, Serge Vernalde, Marc Engels, Ivo Bolsens:
  Hardware/software partitioning of embedded system in OCAPI-xl. 30-35
  
• Shlomo Weiss, Shay Beren:
  HW/SW partitioning of an embedded instruction memory decompressor. 36-41
  
• Karam S. Chatha, Ranga Vemuri:
  MAGELLAN: multiway hardware-software partitioning and scheduling for latency minimization of hierarchical control-dataflow task graphs. 42-47
  
• Denis Hommais, Frédéric Pétrot, Ivan Augé:
  A practical tool box for system level communication synthesis. 48-53
  
• Praveen K. Murthy, Etan G. Cohen, Steve Rowland:
  System canvas: a new design environment for embedded DSP and telecommunication systems. 54-59
  
• Marnix Arnold, Henk Corporaal:
  Designing domain-specific processors. 61-66
  
• Cagdas Akturan, Margarida F. Jacome:
  RS-FDRA: a register sensitive software pipelining algorithm for embedded VLIW processors. 67-72
  
• Pun H. Shiu, Yudong Tan, Vincent John Mooney III:
  A novel parallel deadlock detection algorithm and architecture. 73-78
  
• Peter Petrov, Alex Orailoglu:
  Towards effective embedded processors in codesigns: customizable partitioned caches. 79-84
  
• William Fornaciari, Fabio Salice, Umberto Bondi, Edi Magini:
  Development cost and size estimation starting from high-level specifications. 86-91
  
• Basant Kumar Dwivedi, Jan Hoogerbrugge, Paul Stravers, M. Balakrishnan:
  Exploring design space of parallel realizations: MPEG-2 decoder case study. 92-97
  
• Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto:
  Source-level execution time estimation of C programs. 98-103
  
• Felice Balarin:
  STARS of MPEG decoder: a case study in worst-case analysis of discrete-event systems. 104-108
  
• Manoj Kumar Jain, Lars Wehmeyer, Stefan Steinke, Peter Marwedel, M. Balakrishnan:
  Evaluating register file size in ASIP design. 109-114
  
• Frank Slomka, Matthias Dörfel, Ralf Münzenberger:
  Generating mixing hardware/software systems from SDL specifications. 116-121
  
• Kyoungseok Rha, Kiyoung Choi:
  Area-efficient buffer binding based on a novel two-port FIFO structure. 122-127
  
• José M. Álvarez, Manuel Díaz, Luis Llopis, Ernesto Pimentel, José M. Troya:
  Deriving hard real-time embedded systems implementations directly from SDL specifications. 128-133
  
• Paul Lieverse, Pieter van der Wolf, Ed F. Deprettere:
  A trace transformation technique for communication refinement. 134-139
  
• Dimitris Lioupis, Apostolos Papagiannis, Dionysia Psihogiou:
  A systematic approach to software peripherals for embedded systems. 140-145
  
• Radoslaw Szymanek, Krzysztof Kuchcinski:
  A constructive algorithm for memory-aware task assignment and scheduling. 147-152
  
• Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh, Fadi J. Kurdahi:
  A constraint-based application model and scheduling techniques for power-aware systems. 153-158
  
• Sid Ahmed Ali Touati:
  Optimal acyclic fine-grain scheduling with cache effects for embedded and real time systems. 159-164
  
• Sungtaek Lim, Jihong Kim, Kiyoung Choi:
  Scheduling-based code size reduction in processors with indirect addressing mode. 165-169
  
• Chun Wong, Paul Marchal, Peng Yang:
  Task concurrency management methodology to schedule the MPEG4 IM1 player on a highly parallel processor platform. 170-177
  
• Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi:
  Parameterised system design based on genetic algorithms. 177-182
  
• Paul Pop, Petru Eles, Traian Pop, Zebo Peng:
  Minimizing system modification in an incremental design approach. 183-188
  
• André Chátelain, Yves Mathys, Giovanni Placido, Alberto La Rosa, Luciano Lavagno:
  High-level architectural co-simulation using Esterel and C. 189-194
  
• Sungjoo Yoo, Gabriela Nicolescu, Damien Lyonnard, Amer Baghdadi, Ahmed Amine Jerraya:
  A generic wrapper architecture for multi-processor SoC cosimulation and design. 195-200
  
• Seppo Virtanen, Johan Lilius:
  The TACO protocol processor simulation environment. 201-206
  
• Pao-Ann Hsiung:
  Formal synthesis and code generation of embedded real-time software. 208-213
  
• Johan Cockx:
  Whole program compilation for embedded software: the ADSL experiment. 214-218
  
• Mahmut T. Kandemir, Ismail Kadayif:
  Compiler-directed selection of dynamic memory layouts. 219-224
  
• Yunjian Jiang, Robert K. Brayton:
  Logic optimization and code generation for embedded control applications. 225-229
  
• Royan H. L. Ong, Michael J. Pont:
  Empirical comparison of software-based error detection and correction techniques for embedded systems. 230-235
  
• Vishnu Swaminathan, Krishnendu Chakrabarty, S. Sitharama Iyengar:
  Dynamic I/O power management for hard real-time systems. 237-242
  
• Neal K. Bambha, Shuvra S. Bhattacharyya, Jürgen Teich, Eckart Zitzler:
  Hybrid global/local search strategies for dynamic voltage scaling in embedded multiprocessors. 243-248
  
• Andrea Acquaviva, Luca Benini, Bruno Riccò:
  Processor frequency setting for energy minimization of streaming multimedia application. 249-253
  
• Wen-Tsong Shiue:
  Retargetable compilation for low power. 254-259
  
• William Fornaciari, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria:
  A design framework to efficiently explore energy-delay tradeoffs. 260-265
  

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