13. ASYNC 2007: Berkeley, California, USA

13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 12-14 March 2006, Berkeley, California, USA. IEEE Computer Society 2007, ISBN 978-0-7695-2771-0

High-Speed Links and Signaling

Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia Liran, Ran Ginosar, Avinoam Kolodny:
High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link. 3-14
Jo C. Ebergen, Steve Furber, Arash Saifhashemi:
Notes On Pulse Signaling. 15-24
Suwen Yang, Mark R. Greenstreet, Jihong Ren:
A Jitter Attenuating Timing Chain. 25-38

Asynchronous Applications

Andrew Lines:
The Vortex: A Superscalar Asynchronous Processor. 39-48
Pankaj Golani, Georgios D. Dimou, Mallika Prakash, Peter A. Beerel:
Design of a High-Speed Asynchronous Turbo Decoder. 49-59
Andrew M. Scott, Mark E. Schuelein, Marly Roncken, Jin-Jer Hwan, John Bainbridge, John R. Mawer, David L. Jackson, Andrew Bardsley:
Asynchronous on-Chip Communication: Explorations on the Intel PXA27x Processor Peripheral Bus. 60-72

Verification

Gwen Salaün, Wendelin Serwe, Yvain Thonnart, Pascal Vivet:
Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip. 73-82
Mark B. Josephs:
Gate-level modelling and verification of asynchronous circuits using CSPM and FDR. 83-94

Novel Circuits

Nam-Phuong D. Nguyen, Hiroyuki Kuwahara, Chris J. Myers, James P. Keener:
The Design of a Genetic Muller C-Element. 95-104
Crescenzo D'Alessandro, Andrey Mokhov, Alexandre V. Bystrov, Alexandre Yakovlev:
Delay/Phase Regeneration Circuits. 105-116

Synthesis

Tiberiu Chelcea, Girish Venkataramani, Seth Copen Goldstein:
Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis. 117-128
Melinda Y. Agyekum, Steven M. Nowick:
A Cycle-Based Decomposition Method for Burst-Mode Asynchronous Controllers. 129-142

Test and Measurement

Alex Chow, William S. Coates, David Hopkins:
A Configurable Asynchronous Pseudorandom Bit Sequence Generator. 143-152
Frankie Liu, Ron Ho, Robert J. Drost, Scott Fairbanks:
On-chip samplers for test and debug of asynchronous circuits. 153-162
Nikolaos Minas, David Kinniment, Keith Heron, Gordon Russell:
A High Resolution Flash Time-to-Digital Converter Taking Into Account Process Variability. 163-174

Interfaces

Robert D. Mullins, Simon W. Moore:
Demystifying Data-Driven and Pausible Clocking Schemes. 175-185
Amitava Mitra, William F. McLaughlin, Steven M. Nowick:
Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication. 186-195
Wade L. Williams, Philip E. Madrid, Scott C. Johnson:
Low Latency Clock Domain Transfer for Simultaneously Mesochronous, Plesiochronous and Heterochronous Interfaces. 196-204

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