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ORCID34th ARCS 2021: Virtual Event
- Christian Hochberger
, Lars Bauer, Thilo Pionteck:
Architecture of Computing Systems - 34th International Conference, ARCS 2021, Virtual Event, June 7-8, 2021, Proceedings. Lecture Notes in Computer Science 12800, Springer 2021, ISBN 978-3-030-81681-0
Memory Organization
- Peter M. Kogge, Brian A. Page:
Locality: The 3rd Wall and the Need for Innovation in Parallel Architectures. 3-18 - Thomas Carle, Hugues Cassé:
Static Extraction of Memory Access Profiles for Multi-core Interference Analysis of Real-Time Tasks. 19-34 - João Fabrício Filho, Isaías B. Felzmann, Lucas Francisco Wanner:
Transparent Resilience for Approximate DRAM. 35-50
Heterogeneous Computing
- Lukas Trümper, Julian Miller, Christian Terboven, Matthias S. Müller:
Automatic Mapping of Parallel Pattern-Based Algorithms on Heterogeneous Architectures. 53-67 - Alejandro J. Calderón, Leonidas Kosmidis, Carlos F. Nicolás, Javier de Lasala, Ion Larrañaga:
Assessing and Improving the Suitability of Model-Based Design for GPU-Accelerated Railway Control Systems. 68-83 - Roberto Giorgi, Marco Procaccini, Amin Sahebi:
DRT: A Lightweight Runtime for Developing Benchmarks for a Dataflow Execution Model. 84-100
Instruction Set Transformations
- Alexander Schwarz, Christian Hochberger:
Performance Gain of a Data Flow Oriented ISA as Replacement for Java Bytecode. 103-117 - Ramon Wirsch, Christian Hochberger:
Towards Transparent Dynamic Binary Translation from RISC-V to a CGRA. 118-132
Organic Computing
- Lukas Rosenbauer, David Pätzel, Anthony Stein, Jörg Hähner:
An Organic Computing System for Automated Testing. 135-149 - Eric Hutter, Uwe Brinkschulte:
Evaluating a Priority-Based Task Distribution Strategy for an Artificial Hormone System. 150-164
Low Power Design
- Fabio Montagna, Giuseppe Tagliavini, Davide Rossi, Angelo Garofalo, Luca Benini:
Streamlining the OpenMP Programming Model on Ultra-Low-Power Multi-core MCUs. 167-182 - William B. Toms, John Goodacre, Mikel Luján:
Energy Efficient Power-Management for Out-of-Order Processors Using Cyclic Power-Gating. 183-198
VEFRE Workshop
- Christian Schulz-Hanke:
BCH 2-Bit and 3-Bit Error Correction with Fast Multi-Bit Error Detection. 201-212 - Hao Qiu, Bor-Tyng Lin, Semiu A. Olowogemo, William H. Robinson, Daniel B. Limbrick:
Evaluating Soft Error Mitigation Trade-offs During Early Design Stages. 213-228
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