PACT 2011:
Galveston,
TX,
USA
Lawrence Rauchwerger, Vivek Sarkar (Eds.):
2011 International Conference on Parallel Architectures and Compilation Techniques, PACT 2011, Galveston, TX, USA, October 10-14, 2011.
IEEE Computer Society 2011, ISBN 978-1-4577-1794-9 
Scheduling
Coherence
- Hongzhou Zhao, Arrvindh Shriraman, Sandhya Dwarkadas, Vijayalakshmi Srinivasan:
SPATL: Honey, I Shrunk the Coherence Directory.
33-44
- Hemayet Hossain, Sandhya Dwarkadas, Michael C. Huang:
POPS: Coherence Protocol Optimization for Both Private and Shared Data.
45-55
- Jun Lee, Jungwon Kim, Junghyun Kim, Sangmin Seo, Jaejin Lee:
An OpenCL Framework for Homogeneous Manycores with No Hardware Cache Coherence.
56-67
High-Level Programming Frameworks
Power Efficiency
- Ganesh S. Dasika, Ankit Sethia, Trevor N. Mudge, Scott A. Mahlke:
PEPSC: A Power-Efficient Processor for Scientific Computing.
101-110
- Jungseob Lee, Vijay Sathisha, Michael J. Schulte, Katherine Compton, Nam Sung Kim:
Improving Throughput of Power-Constrained GPUs Using Dynamic Voltage/Frequency and Core Scaling.
111-120
- Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu, Omer Khan:
Performance Per Watt Benefits of Dynamic Core Morphing in Asymmetric Multicores.
121-130
Best Paper Session
- Nikolas Ioannou, Michael Kauschke, Matthias Gries, Marcelo Cintra:
Phase-Based Application-Driven Hierarchical Power Management on the Single-chip Cloud Computer.
131-142
- Yuanrui Zhang, Wei Ding, Jun Liu, Mahmut T. Kandemir:
Optimizing Data Layouts for Parallel Computation on Multicores.
143-154
- Byn Choi, Rakesh Komuravelli, Hyojin Sung, Robert Smolinski, Nima Honarmand, Sarita V. Adve, Vikram S. Adve, Nicholas P. Carter, Ching-Tsun Chou:
DeNovo: Rethinking the Memory Hierarchy for Disciplined Parallelism.
155-166
PACT 2011 Posters
- Zhiwei Xiao, Haibo Chen, Binyu Zang:
A Hierarchical Approach to Maximizing MapReduce Efficiency.
167-168
- Serge Guelton, Adrien Guinet, Ronan Keryell:
Building Retargetable and Efficient Compilers for Multimedia Instruction Sets.
169-170
- Wei Ding, Jithendra Srinivas, Mahmut T. Kandemir, Mustafa Karaköy:
Compiler Directed Data Locality Optimization for Multicore Architectures.
171-172
- Xin Xu, Man-Lap Li:
CriticalFault: Amplifying Soft Error Effect Using Vulnerability-Driven Injection.
173-174
- Gagandeep S. Sachdev, Kshitij Sudan, Mary W. Hall, Rajeev Balasubramonian:
Understanding the Behavior of Pthread Applications on Non-Uniform Cache Architectures.
175-176
- Junghoon Lee, Minjeong Shin, Hanjoon Kim, John Kim, Jaehyuk Huh:
Exploiting Mutual Awareness between Prefetchers and On-chip Networks in Multi-cores.
177-178
- Neal Clayton Crago, Sanjay J. Patel:
Decoupled Architectures as a Low-Complexity Alternative to Out-of-order Execution.
179-180
- Wenjing Ma, Sriram Krishnamoorthy, Gagan Agrawal:
Parameterized Micro-benchmarking: An Auto-tuning Approach for Complex Applications.
181-182
- Manu Awasthi, David W. Nellans, Rajeev Balasubramonian, Al Davis:
Prediction Based DRAM Row-Buffer Management in the Many-Core Era.
183-184
- Zhe Wang, Daniel A. Jiménez:
Program Interferometry.
185-186
- Syed Minhaj Hassan, Dhruv Choudhary, Mitchelle Rasquinha, Sudhakar Yalamanchili:
Regulating Locality vs. Parallelism Tradeoffs in Multiple Memory Controller Environments.
187-188
- Nagendra Gulur, R. Manikantan, R. Govindarajan, Mahesh Mehendale:
Row-Buffer Reorganization: Simultaneously Improving Performance and Reducing Energy in DRAMs.
189-190
- Chongmin Li, Haixia Wang, Yibo Xue, Dongsheng Wang, Jian Li:
Scalable Proximity-Aware Cache Replication in Chip Multiprocessors.
191-192
- Baik Song An, Ki Hwan Yum, Eun Jung Kim:
Scalable and Efficient Bounds Checking for Large-Scale CMP Environments.
193-194
- Yonggon Kim, Hyunseok Lee, John Kim:
An Alternative Memory Access Scheduling in Manycore Accelerators.
195-196
- Javier Lira, Timothy M. Jones, Carlos Molina, Antonio González:
Beforehand Migration on D-NUCA Caches.
197-198
- Gulay Yalcin, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero:
SymptomTM: Symptom-Based Error Detection and Recovery Using Hardware Transactional Memory.
199-200
- Jie Chen, Zachary Winter, Guru Venkataramani, H. Howie Huang:
rPRAM: Exploring Redundancy Techniques to Improve Lifetime of PCM-based Main Memory.
201-202
- Anurag Negi, Per Stenström, J. Rubén Titos Gil, Manuel E. Acacio, José M. García:
Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory.
203-204
- Dimitris Kaseridis, Muhammad Faisal Iqbal, Jeffrey Stuecheli, Lizy Kurian John:
MCFQ: Leveraging Memory-level Parallelism and Application's Cache Friendliness for Efficient Management of Quasi-partitioned Last-level Caches.
205-206
- Ping Zhou, Bo Zhao, Youtao Zhang, Jun Yang, Yiran Chen:
MRAC: A Memristor-based Reconfigurable Framework for Adaptive Cache Replacement.
207-208
PACT 2011 SRC Posters
- Yingying Tian, Daniel A. Jiménez:
Sampling Temporal Touch Hint (STTH) Inclusive Cache Management Policy.
209
- Zhe Wang, Daniel A. Jiménez:
Exploiting Rank Idle Time for Scheduling Last-Level Cache Writeback.
210
- Daniel A. Orozco:
TIDeFlow: A Parallel Execution Model for High Performance Computing Programs.
211
- Samira Manabi Khan, Daniel A. Jiménez:
Decoupled Cache Segmentation: Mutable Policy with Automated Bypass.
212
- Jung-Ho Park, Choonki Jang, Jaejin Lee:
A Software-Managed Coherent Memory Architecture for Manycores.
213
- Alejandro Valero, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato:
Improving Last-Level Cache Performance by Exploiting the Concept of MRU-Tour.
214
- Baojiang Shou, Xionghui Hou, Li Chen:
A Compiler-assisted Runtime-prefetching Scheme for Heterogenous Platforms.
215
- Alexandros Tzannes, Rajeev Barua, Uzi Vishkin:
Improving Run-Time Scheduling for General-Purpose Parallel Code.
216
- Xiaoming Gu:
Collaborative Caching for Unknown Cache Sizes.
217
- Sayan Ghosh, Barbara Chapman:
Programming Strategies for GPUs and their Power Consumption.
218
- Rance Rodrigues, Israel Koren, Sandip Kundu:
An Architecture to Enable Lifetime Full Chip Testability in Chip Multiprocessors.
219
- Zhijia Zhao, Bo Wu:
Probabilistic Models Towards Optimal Speculation of DFA Applications.
220
Transactional Memory
Locality
- Bo Wu, Eddy Z. Zhang, Xipeng Shen:
Enhancing Data Locality for Dynamic Simulations through Asynchronous Data Transformations and Adaptive Control.
243-252
- Sangmin Seo, Junghyun Kim, Jaejin Lee:
SFMalloc: A Lock-Free and Mostly Synchronization-Free Dynamic Memory Allocator for Manycores.
253-263
- Meng-Ju Wu, Donald Yeung:
Coherent Profiles: Enabling Efficient Reuse Distance Analysis of Multicore Scaling for Loop-based Parallel Programs.
264-275
Customized Processors
- Naser Sedaghati, Renji Thomas, Louis-Noël Pouchet, Radu Teodorescu, P. Sadayappan:
StVEC: A Vector Instruction Extension for High Performance Stencil Computation.
276-287
- Jiangzhou He, Wenguang Chen, Guangri Chen, Weimin Zheng, Zhizhong Tang, Handong Ye:
OpenMDSP: Extending OpenMP to Program Multi-Core DSP.
288-297
- Konstantinos Aisopos, Andrew DeOrio, Li-Shiuan Peh, Valeria Bertacco:
ARIADNE: Agnostic Reconfiguration in a Disconnected Network Environment.
298-309
SPMD Analysis
- Ziyu Guo, Eddy Zheng Zhang, Xipeng Shen:
Correctly Treating Synchronizations in Compiling Fine-Grained SPMD-Threaded Programs for CPU.
310-319
- Bruno Coutinho, Diogo Sampaio, Fernando Magno Quintão Pereira, Wagner Meira Jr.:
Divergence Analysis and Optimizations.
320-329
- Anh Vo, Ganesh Gopalakrishnan, Robert M. Kirby, Bronis R. de Supinski, Martin Schulz, Greg Bronevetsky:
Large Scale Verification of MPI Programs Using Lamport Clocks with Lazy Update.
330-339
Memory Hierarchies
- Carlos Villavieja, Vasileios Karakostas, Lluís Vilanova, Yoav Etsion, Alex Ramírez, Avi Mendelson, Nacho Navarro, Adrián Cristal, Osman S. Unsal:
DiDi: Mitigating the Performance Impact of TLB Shootdowns Using a Shared TLB Directory.
340-349
- Xiaoya Xiang, Bin Bao, Chen Ding, Yaoqing Gao:
Linear-time Modeling of Program Working Set in Shared Cache.
350-360
- Adrià Armejach, Azam Seyedi, J. Rubén Titos Gil, Ibrahim Hur, Adrián Cristal, Osman S. Unsal, Mateo Valero:
Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory.
361-371
Compiler Optimizations
Potpourri
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