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Publication search results
found 41 matches
- 2017
- Almutaz Adileh, Stijn Eyerman, Aamer Jaleel, Lieven Eeckhout:
Mind The Power Holes: Sifting Operating Points in Power-Limited Heterogeneous Multicores. IEEE Comput. Archit. Lett. 16(1): 56-59 (2017) - Hossein Ahmadvand, Maziar Goudarzi:
Using Data Variety for Efficient Progressive Big Data Processing in Warehouse-Scale Computers. IEEE Comput. Archit. Lett. 16(2): 166-169 (2017) - Abdel-Hameed A. Badawy, Donald Yeung:
Guiding Locality Optimizations for Graph Computations via Reuse Distance Analysis. IEEE Comput. Archit. Lett. 16(2): 119-122 (2017) - Mohammad Bakhshalipour, Pejman Lotfi-Kamran, Hamid Sarbazi-Azad:
An Efficient Temporal Data Prefetcher for L1 Caches. IEEE Comput. Archit. Lett. 16(2): 99-102 (2017) - Nathan Beckmann, Daniel Sánchez:
Cache Calculus: Modeling Caches through Differential Equations. IEEE Comput. Archit. Lett. 16(1): 1-5 (2017) - Amirali Boroumand, Saugata Ghose, Minesh Patel, Hasan Hassan, Brandon Lucia, Kevin Hsieh, Krishna T. Malladi, Hongzhong Zheng, Onur Mutlu:
LazyPIM: An Efficient Cache Coherence Mechanism for Processing-in-Memory. IEEE Comput. Archit. Lett. 16(1): 46-50 (2017) - Trevor E. Carlson, Kim-Anh Tran, Alexandra Jimborean, Konstantinos Koukos, Magnus Själander, Stefanos Kaxiras:
Transcending Hardware Limits with Software Out-of-Order Processing. IEEE Comput. Archit. Lett. 16(2): 162-165 (2017) - Li-Jhan Chen, Hsiang-Yun Cheng, Po-Han Wang, Chia-Lin Yang:
Improving GPGPU Performance via Cache Locality Aware Thread Block Scheduling. IEEE Comput. Archit. Lett. 16(2): 127-131 (2017) - Liang Feng, Hao Liang, Sharad Sinha, Wei Zhang:
HeteroSim: A Heterogeneous CPU-FPGA Simulator. IEEE Comput. Archit. Lett. 16(1): 38-41 (2017) - James Garland, David Gregg:
Low Complexity Multiply Accumulate Unit for Weight-Sharing Convolutional Neural Networks. IEEE Comput. Archit. Lett. 16(2): 132-135 (2017) - Mark Gottscho, Mohammed Shoaib, Sriram Govindan, Bikash Sharma, Di Wang, Puneet Gupta:
Measuring the Impact of Memory Errors on Application Performance. IEEE Comput. Archit. Lett. 16(1): 51-55 (2017) - Dong-Ik Jeon, Ki-Seok Chung:
CasHMC: A Cycle-Accurate Simulator for Hybrid Memory Cube. IEEE Comput. Archit. Lett. 16(1): 10-13 (2017) - Hoda Naghibi Jouybari, Nael B. Abu-Ghazaleh:
Covert Channels on GPGPUs. IEEE Comput. Archit. Lett. 16(1): 22-25 (2017) - Patrick Judd, Jorge Albericio, Andreas Moshovos:
Stripes: Bit-Serial Deep Neural Network Computing. IEEE Comput. Archit. Lett. 16(1): 80-83 (2017) - Myoungsoo Jung:
NearZero: An Integration of Phase Change Memory with Multi-Core Coprocessor. IEEE Comput. Archit. Lett. 16(2): 136-140 (2017) - Samira Manabi Khan, Chris Wilkerson, Donghyuk Lee, Alaa R. Alameldeen, Onur Mutlu:
A Case for Memory Content-Based Detection and Mitigation of Data-Dependent Failures in DRAM. IEEE Comput. Archit. Lett. 16(2): 88-93 (2017) - Junghee Lee, Kalidas Ganesh, Hyuk-Jun Lee, Youngjae Kim:
FeSSD: A Fast Encrypted SSD Employing On-Chip Access-Control Memory. IEEE Comput. Archit. Lett. 16(2): 115-118 (2017) - Madhavan Manivannan, Miquel Pericàs, Vassilis Papaefstathiou, Per Stenström:
Runtime-Assisted Global Cache Management for Task-Based Parallel Programs. IEEE Comput. Archit. Lett. 16(2): 145-148 (2017) - David A. González Márquez, Adrián Cristal Kestelman, Esteban E. Mocskos:
Mth: Codesigned Hardware/Software Support for Fine Grain Threads. IEEE Comput. Archit. Lett. 16(1): 64-67 (2017) - Jorge A. Martínez, Juan Antonio Maestro, Pedro Reviriego:
A Scheme to Improve the Intrinsic Error Detection of the Instruction Set Architecture. IEEE Comput. Archit. Lett. 16(2): 103-106 (2017) - Amirhossein Mirhosseini, Aditya Agrawal, Josep Torrellas:
Survive: Pointer-Based In-DRAM Incremental Checkpointing for Low-Cost Data Persistence and Rollback-Recovery. IEEE Comput. Archit. Lett. 16(2): 153-157 (2017) - Sparsh Mittal, Jeffrey S. Vetter, Lei Jiang:
Addressing Read-Disturbance Issue in STT-RAM by Data Compression and Selective Duplication. IEEE Comput. Archit. Lett. 16(2): 94-98 (2017) - Tomer Y. Morad, Gil Shomron, Mattan Erez, Avinoam Kolodny, Uri C. Weiser:
Optimizing Read-Once Data Flow in Big-Data Applications. IEEE Comput. Archit. Lett. 16(1): 68-71 (2017) - Arthur Perais, André Seznec:
Storage-Free Memory Dependency Prediction. IEEE Comput. Archit. Lett. 16(2): 149-152 (2017) - Sandro Pinto, Jorge Pereira, Tiago Gomes, Mongkol Ekpanyapong, Adriano Tavares:
Towards a TrustZone-Assisted Hypervisor for Real-Time Embedded Systems. IEEE Comput. Archit. Lett. 16(2): 158-161 (2017) - Gokul Subramanian Ravi, Mikko H. Lipasti:
Timing Speculation in Multi-Cycle Data Paths. IEEE Comput. Archit. Lett. 16(1): 84-87 (2017) - Hiroshi Sasaki, Alper Buyuktosunoglu, Augusto Vega, Pradip Bose:
Mitigating Power Contention: A Scheduling Based Approach. IEEE Comput. Archit. Lett. 16(1): 60-63 (2017) - Hiroshi Sasaki, Fang-Hsiang Su, Teruo Tanimoto, Simha Sethumadhavan:
Heavy Tails in Program Structure. IEEE Comput. Archit. Lett. 16(1): 34-37 (2017) - Seyed Mohammad Seyedzadeh, Alex K. Jones, Rami G. Melhem:
Counter-Based Tree Structure for Row Hammering Mitigation in DRAM. IEEE Comput. Archit. Lett. 16(1): 18-21 (2017) - Young Hoon Son, Hyunyoon Cho, Yuhwan Ro, Jae W. Lee, Jung Ho Ahn:
SALAD: Achieving Symmetric Access Latency with Asymmetric DRAM Architecture. IEEE Comput. Archit. Lett. 16(1): 76-79 (2017)
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