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Publication search results
found 132 matches
- 1990
- Prathima Agrawal, William J. Dally:
A hardware logic simulation system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(1): 19-29 (1990) - Prathima Agrawal, Scott H. Robinson, Thomas G. Szymanski:
Automatic modeling of switch-level networks using partial orders [MOS circuits]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(7): 696-707 (1990) - Asim J. Al-Khalili, Yong Zhu, Dhamin Al-Khalili:
A module generator for optimized CMOS buffers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(10): 1028-1046 (1990) - Valery Axelrad:
Fourier method modeling of semiconductor devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(11): 1225-1237 (1990) - Ronald F. Ayres:
Completely automatic completion of VLSI designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(2): 194-202 (1990) - Jacques Benkoski, E. Vanden Meersch, Luc J. M. Claesen, Hugo De Man:
Timing verification using statically sensitizable paths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(10): 10723-10784 (1990) - Wolfgang Bergner, Roland Kircher:
SITAR-an efficient 3-D simulator for optimization of nonplanar trench structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(11): 1184-1188 (1990) - Debashis Bhattacharya, John P. Hayes:
Designing for high-level test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(7): 752-766 (1990) - Nripendra N. Biswas:
On covering distant minterms by the camp algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(7): 786-789 (1990) - Richard Booth, Marvin White:
Simulation of a MOS transistor with spatially nonuniform channel parameters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(12): 1354-1357 (1990) - Angelo Brambilla, Enrico Dallago:
A circuit-level simulation model of PNPN devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(12): 1254-1264 (1990) - Gregory T. Brauns, R. J. Bishop, Michael Steer, John J. Paulos, Sasan H. Ardalan:
Table-based modeling of delta-sigma modulators using ZSIM. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(2): 142-150 (1990) - Forrest Brewer, Daniel D. Gajski:
Chippe: a system for constraint driven behavioral synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(7): 681-695 (1990) - Srimat T. Chakradhar, Michael L. Bushnell, Vishwani D. Agrawal:
Toward massively parallel automatic test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(9): 981-994 (1990) - Sreejit Chakravarty, S. S. Ravi:
Computing optimal test sequences from complete test sets for stuck-open faults in CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(3): 329-331 (1990) - Pak K. Chan, Kevin Karplus:
Computing signal delay in general RC networks by tree/link partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(8): 898-902 (1990) - D. Y. Cheng, J. T. Deutsch, Robert W. Dutton:
'Defensive programming' in the rapid development of a parallel scientific program. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(6): 665-669 (1990) - Charles C. Chiang, Majid Sarrafzadeh, Chak-Kuen Wong:
Global routing based on Steiner min-max trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(12): 1318-1325 (1990) - Shiu-Kai Chin, Edward P. Stabler:
Synthesis of arithmetic hardware using hardware metafunctions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(8): 793-803 (1990) - S. Chowdhury, Javed Sabir Barkatullah:
Estimation of maximum currents in MOS IC logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(6): 642-654 (1990) - James P. Cohoon, Dana S. Richards, Jeffrey S. Salowe:
An optimal Steiner tree algorithm for a net whose terminals lie on the perimeter of a rectangle. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(4): 398-407 (1990) - Jason Cong, C. L. Liu:
Over-the-cell channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(4): 408-418 (1990) - Maurizio Damiani, Piero Olivo, Michele Favalli, Silvia Ercolani, Bruno Riccò:
Aliasing in signature analysis testing with multiple input shift registers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(12): 1344-1353 (1990) - Rob Dekker, Frans P. M. Beenker, Loek Thijssen:
A realistic fault model and test algorithms for static random access memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(6): 567-572 (1990) - Stephen R. Demba, Ernst G. Ulrich, Karen Panetta Lentz, David Giramma:
Experiences with concurrent fault simulation of diagnostic programs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(6): 621-628 (1990) - Michael Demjanenko, Shambhu J. Upadhyaya:
Yield enhancement of field programmable logic arrays by inherent component redundancy. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(8): 876-884 (1990) - An-Chang Deng, Yan-Chyuan Shiau:
Generic linear RC delay modeling for digital CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(4): 367-376 (1990) - Bulent I. Dervisoglu:
Application of scan hardware and software for debug and diagnostics in a workstation environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(6): 612-620 (1990) - Srinivas Devadas, Hi-Keung Tony Ma:
Easily testable PLA-based finite state machines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(6): 604-611 (1990) - Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli:
Irredundant sequential machines via optimal logic synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(1): 8-18 (1990)
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