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Publication search results
found 28 matches
- 2006
- Ben A. Abderazek, Sotaro Kawata, Masahiro Sowa:
Design and architecture for an embedded 32-bit QueueCore. J. Embed. Comput. 2(2): 191-205 (2006) - Fumio Arakawa, Makoto Ishikawa, Yuki Kondo, Tatsuya Kamei, Osamu Nishii, Toshihiro Hattori:
SH-X: An embedded processor core for consumer appliances. J. Embed. Comput. 2(1): 83-90 (2006) - Maxime Van Assche, Joël Goossens, Raymond R. Devillers:
Joint garbage collection and hard real-time scheduling. J. Embed. Comput. 2(3-4): 313-326 (2006) - Sandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete:
Embedded processors and systems: Architectural issues and solutions for emerging applications. J. Embed. Comput. 2(1): 1-3 (2006) - Sandro Bartolini, Roberto Giorgi:
Issues in Embedded Single-Chip Multicore Architectures. J. Embed. Comput. 2(2): 137-139 (2006) - Yul Chu, Arul Sandeep Gade, Abhishek Bhaduri:
A low-power cache scheme for embedded computing. J. Embed. Comput. 2(2): 261-269 (2006) - Haakon Dybdahl, Per Gunnar Kjeldsberg, Marius Grannæs, Lasse Natvig:
Destructive-read in embedded DRAM, impact on power consumption. J. Embed. Comput. 2(2): 249-260 (2006) - Hamed Fatemi, Bart Mesman, Henk Corporaal, Twan Basten, Richard P. Kleihorst:
RC-SIMD: Reconfigurable communication SIMD architecture for image processing applications. J. Embed. Comput. 2(2): 167-179 (2006) - Nathan Fisher, Sanjoy K. Baruah:
A fully polynomial-time approximation scheme for feasibility analysis in static-priority systems with bounded relative deadlines. J. Embed. Comput. 2(3-4): 291-299 (2006) - Patrick Anthony La Fratta, James M. Baker Jr.:
Exploring power reduction options for a single-chip multiprocessor through system-level modeling. J. Embed. Comput. 2(2): 235-247 (2006) - Seiichiri Fujii, Akihito Sakanaka, Akihiro Chiyonobu, Toshinori Sato:
A leakage-energy-reduction technique for cache memories in embedded processors. J. Embed. Comput. 2(1): 49-55 (2006) - Abdoulaye Gamatié, Thierry Gautier, Paul Le Guernic:
Synchronous design of avionic applications based on model refinement. J. Embed. Comput. 2(3-4): 273-289 (2006) - Pei Gu, Uzi Vishkin:
Case study of gate-level logic simulation on an extremely fine-grained chip multiprocessor. J. Embed. Comput. 2(2): 181-190 (2006) - Steven Martin, Pascale Minet, Laurent George:
Improving fixed priority schedulability with dynamic priority as secondary criterion. J. Embed. Comput. 2(3-4): 327-345 (2006) - Aleksandar Milenkovic, Milena Milenkovic, Emil Jovanov:
An efficient runtime instruction block verification for secure embedded systems. J. Embed. Comput. 2(1): 57-76 (2006) - Afrin Naz, Krishna M. Kavi, Wentong Li, Philip H. Sweany:
Tiny split data-caches make big performance impact for embedded applications. J. Embed. Comput. 2(2): 207-219 (2006) - Timothy W. O'Neil, Edwin Hsing-Mean Sha:
Time-constrained loop scheduling with minimal resources. J. Embed. Comput. 2(1): 103-117 (2006) - John Y. Oliver, Ravishankar Rao, Diana Franklin, Frederic T. Chong, Venkatesh Akella:
Synchroscalar: Evaluation of an embedded, multi-core architecture for media applications. J. Embed. Comput. 2(2): 157-166 (2006) - Frédéric Ridouard, Pascal Richard, Francis Cottet, Karim Traore:
Some results on scheduling tasks with self-suspensions. J. Embed. Comput. 2(3-4): 301-312 (2006) - David Ródenas, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, George Almási, Calin Cascaval, José G. Castaños, José E. Moreira:
Exploiting multilevel parallelism using OpenMP on a massive multithreaded architecture. J. Embed. Comput. 2(2): 141-155 (2006) - Rishi Saket, Nicolas Navet:
Frame packing algorithms for automotive applications. J. Embed. Comput. 2(1): 93-102 (2006) - Henrik Schiøler, Jens Dalsgaard Nielsen, Kim Guldstrand Larsen, Jan Jakob Jessen:
CyNC: A method for real time analysis of systems with cyclic data flows. J. Embed. Comput. 2(3-4): 347-360 (2006) - Alex Settle, Dan Connors, Enric Gibert, Antonio González:
A dynamically reconfigurable cache for multithreaded processors. J. Embed. Comput. 2(2): 221-233 (2006) - G. Surendra, Subhasis Banerjee, S. K. Nandy:
Instruction Reuse in SPEC, media and packet processing benchmarks: A comparative study of power, performance and related microarchitectural optimizations. J. Embed. Comput. 2(1): 15-34 (2006) - Javier Verdú, Jorge García-Vidal, Mario Nemirovsky, Mateo Valero:
The impact of traffic aggregation on the memory performance of networking applications. J. Embed. Comput. 2(1): 77-82 (2006) - Gang Wang, Wenrui Gong, Ryan Kastner:
Application partitioning on programmable platforms using the ant colony optimization. J. Embed. Comput. 2(1): 119-136 (2006) - Sami Yehia, Jean-Francois Collard, Olivier Temam:
Load squared: Adding logic close to memory to reduce the latency of indirect loads in embedded and general systems. J. Embed. Comput. 2(1): 5-14 (2006) - Wei Zhang:
Compiler-guided next sub-bank prediction for reducing instruction cache leakage energy. J. Embed. Comput. 2(1): 35-48 (2006)
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