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Publication search results
found 21 matches
- 2010
- Dominik Auras, Sylvain Girbal, Hugues Berry, Olivier Temam, Sami Yehia:
CMA: Chip multi-accelerator. SASP 2010: 8-15 - Ahmed O. El-Rayis, Tughrul Arslan, Ahmet T. Erdogan:
A processing engine for GPS correlation. SASP 2010: 44-49 - Khodor Ahmad Fawaz, Tughrul Arslan, Sami Khawam, Mark Muir, Ioannis Nousias, Iain Lindsay, Ahmet T. Erdogan:
A dynamically reconfigurable asynchronous processor. SASP 2010: 93-96 - Jingtong Hu, Chun Jason Xue, Wei-Che Tseng, Qingfeng Zhuge, Edwin Hsing-Mean Sha:
Minimizing write activities to non-volatile memory via scheduling and recomputation. SASP 2010: 101-106 - Jer-Min Jou, Yun-Lung Lee, Sih-Sian Wu:
Efficient design and generation of a multi-facet arbiter. SASP 2010: 111-114 - Ji Kong, Peilin Liu, Xianmin Chen, Jin Wang, Xingguang Pan, Jun Wang, He Xiao, Zhenqi Wei, Rendong Ying:
Next-generation consumer audio application specific embedded processor. SASP 2010: 1-7 - Ruby B. Lee, Yu-Yuan Chen:
Processor accelerator for AES. SASP 2010: 16-21 - Pei Liu, Ahmed Hemani:
A Coarse Grain Reconfigurable Architecture for sequence alignment problems in bio-informatics. SASP 2010: 50-57 - Jason Loew, Dmitry Ponomarev, Patrick H. Madden:
Customized architectures for faster route finding in GPS-based navigation systems. SASP 2010: 36-43 - Thomas Marconi, Jae Young Hur, Koen Bertels, Georgi Gaydadjiev:
A novel configuration circuit architecture to speedup reconfiguration and relocation for partially reconfigurable devices. SASP 2010: 87-92 - Naotaka Maruyama, Tohru Ishihara, Hiroto Yasuura:
An RTOS in hardware for energy efficient software-based TCP/IP processing. SASP 2010: 58-63 - Nicholas Moore, Miriam Leeser, Laurie A. Smith King:
Efficient template matching with variable size templates in CUDA. SASP 2010: 77-80 - David Novo, Angeliki Kritikakou, Praveen Raghavan, Liesbet Van der Perre, Jos Huisken, Francky Catthoor:
Ultra low energy Domain Specific Instruction-set Processor for on-line surveillance. SASP 2010: 30-35 - Mathew Paul, Peter Petrov:
I-cache configurability for temperature reduction through replicated cache partitioning. SASP 2010: 81-86 - Yi Shan, Tianji Wu, Yu Wang, Bo Wang, Zilong Wang, Ningyi Xu, Huazhong Yang:
FPGA and GPU implementation of large scale SpMV. SASP 2010: 64-70 - Michael Steffen, Joseph Zambreno:
A hardware pipeline for accelerating ray traversal algorithms on streaming processors. SASP 2010: 22-29 - Jelena Trajkovic, Daniel D. Gajski:
Early performance-cost estimation of application-specific data path pipelining. SASP 2010: 107-110 - Antonino Tumeo, Oreste Villa:
Accelerating DNA analysis applications on GPU clusters. SASP 2010: 71-76 - Dan Upton, Kim M. Hazelwood:
Design of a custom VEE core in a chip multiprocessor. SASP 2010: 97-100 - Hui-Shan Wang, I-Wei Wu, Jean Jyh-Jiun Shann, Chung-Ping Chung:
Reconfigurable custom functional unit generation and exploitation in multiple-issue processors. SASP 2010: 115-118 - IEEE 8th Symposium on Application Specific Processors, SASP 2010, Anaheim, CA, USA, June 13-14, 2010. IEEE Computer Society 2010, ISBN 978-1-4244-7952-8 [contents]
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