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Publication search results
found 64 matches
- 2006
- Mythri Alle, Jayanta Biswas, S. K. Nandy:
High Performance VLSI Architecture Design for H.264 CAVLC Decoder. ASAP 2006: 317-322 - Jeffrey M. Arnold:
Software Configurable Processors. ASAP 2006: 45-49 - Florin Balasa, Per Gunnar Kjeldsberg, Martin Palkovic, Arnout Vandecappelle, Francky Catthoor:
Loop Transformation Methodologies for Array-Oriented Memory Management. ASAP 2006: 205-212 - Aydin O. Balkan, Gang Qu, Uzi Vishkin:
A Mesh-of-Trees Interconnection Network for Single-Chip Parallel Processing. ASAP 2006: 73-80 - Guido Bertoni, Luca Breveglieri, Roberto Farina, Francesco Regazzoni:
Speeding Up AES By Extending a 32 bit Processor Instruction Set. ASAP 2006: 275-282 - Aasavari Bhave, Eurípides Montagne, Edgar Granados:
Describing Quantum Circuits with Systolic Arrays. ASAP 2006: 109-113 - Youcef Bouchebaba, Gabriela Nicolescu, El Mostapha Aboulhamid, Fabien Coelho:
Buffer and register allocation for memory space optimization. ASAP 2006: 283-290 - Humberto Calderon, Stamatis Vassiliadis:
Reconfigurable Fixed Point Dense and Sparse Matrix-Vector Multiply/Add Unit. ASAP 2006: 311-316 - Peter R. Cappello:
Multicore processors as Array Processors: Research Opportunities. ASAP 2006: 169-172 - Ivan D. Castellanos, James E. Stine:
A 64-bit Decimal Floating-Point Comparator. ASAP 2006: 138-144 - Herwin Chan, Miguel Griot, Andres I. Vila Casado, Richard D. Wesel, Ingrid Verbauwhede:
High Speed Channel Coding Architectures for the Uncoordinated OR Channel. ASAP 2006: 265-268 - Philippe Clauss, Bénédicte Kenmei:
Polyhedral Modeling and Analysis of Memory Access Profiles. ASAP 2006: 191-198 - Masoud Daneshtalab, Ashkan Sobhani, Ali Afzali-Kusha, Omid Fatemi, Zainalabedin Navabi:
NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm. ASAP 2006: 33-38 - Ed F. Deprettere, Todor P. Stefanov, Shuvra S. Bhattacharyya, Mainak Sen:
Affine Nested Loop Programs and their Binary Parameterized Dataflow Graph Counterparts. ASAP 2006: 186-190 - Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos:
An Energy-Delay Efficient Subword Permutation Unit. ASAP 2006: 245-252 - Guerric Meurice de Dormale, Renaud Ambroise, David Bol, Jean-Jacques Quisquater, Jean-Didier Legat:
Low-Cost Elliptic Curve Digital Signature Coprocessor for Smart Cards. ASAP 2006: 347-353 - Hritam Dutta, Frank Hannig, Jürgen Teich, Benno Heigl, Heinz Hornegger:
A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing. ASAP 2006: 331-340 - Carl Ebeling:
Configurable Computing Platforms - Promises, Promises. ASAP 2006: 3-4 - Chuan He, Guan Qin, Mi Lu, Wei Zhao:
An Efficient Implementation of High-Accuracy Finite Difference Computing Engine on FPGAs. ASAP 2006: 95-98 - Yedidya Hilewitz, Ruby B. Lee:
Fast Bit Compression and Expansion with Parallel Extract and Parallel Deposit Instructions. ASAP 2006: 65-72 - Shaoxiong Hua, Pushkin R. Pari, Gang Qu:
Dual-Processor Design of Energy Efficient Fault-Tolerant System. ASAP 2006: 239-244 - Richard Hughey, Andrea Di Blas:
The UCSC Kestrel Application-Unspecific Processor. ASAP 2006: 163-168 - Pablo Ituero, Marisa López-Vallejo:
New Schemes in Clustered VLIW Processors Applied to Turbo Decoding. ASAP 2006: 291-296 - Francisco J. Jaime, Julio Villalba, Javier Hormigo, Emilio L. Zapata:
Pipelined Range Reduction for Floating Point Numbers. ASAP 2006: 145-152 - Graham A. Jullien:
Array Processing Using Alternate Arithmetic - A 20 Year Legacy. ASAP 2006: 199-204 - Marjan Karkooti, Predrag Radosavljevic, Joseph R. Cavallaro:
Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation. ASAP 2006: 360-367 - DaeGon Kim, Sanjay V. Rajopadhye:
An Improved Systolic Architecture for LU Decomposition. ASAP 2006: 231-238 - Ming-Yung Ko, Claudiu Zissulescu, Sebastian Puthenpurayil:
Parameterized Looped Schedules for Compact Representationof Execution Sequences. ASAP 2006: 223-230 - Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, Ingrid Verbauwhede:
Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip. ASAP 2006: 15-18 - Yong Ki Lee, Herwin Chan, Ingrid Verbauwhede:
Throughput Optimized SHA-1 Architecture Using Unfolding Transformation. ASAP 2006: 354-359
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retrieved on 2024-05-31 13:17 CEST from data curated by the dblp team
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