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Publication search results
found 20 matches
- 2023
- Yufeng Zhou, Alan L. Cox, Sandhya Dwarkadas, Xiaowan Dong:
The Impact of Page Size and Microarchitecture on Instruction Address Translation Overhead. ACM Trans. Archit. Code Optim. 20(3): 38:1-38:25 (2023) - 2022
- Pengfei Wu, Zheng Wang, Zhiming Pan, Weilun Wang:
LIPFD-NPU: Low-overhead Instruction-driven Permanent Fault Detection for Neural Processing Unit. ICTA 2022: 22-23 - 2019
- Yehia Arafa, Abdel-Hameed A. Badawy, Gopinath Chennupati, Nandakishore Santhi, Stephan J. Eidenbenz:
Low Overhead Instruction Latency Characterization for NVIDIA GPGPUs. HPEC 2019: 1-8 - Yufeng Zhou, Xiaowan Dong, Alan L. Cox, Sandhya Dwarkadas:
On the Impact of Instruction Address Translation Overhead. ISPASS 2019: 106-116 - 2018
- Toru Koizumi, Satoshi Nakae, Akifumi Fukuda, Hidetsugu Irie, Shuichi Sakai:
Reduction of Instruction Increase Overhead by STRAIGHT Compiler. CANDAR Workshops 2018: 92-98 - Andrzej Nowak, Pawel Szostek, Ahmad Yasin, Willy Zwaenepoel:
Low-Overhead Dynamic Instruction Mix Generation Using Hybrid Basic Block Profiling. ISPASS 2018: 189-198 - Navid Emamdoost, Stephen McCamant:
The Effect of Instruction Padding on SFI Overhead. CoRR abs/1803.00169 (2018) - 2017
- Alireza Namazi, Meisam Abdollahi, Saeed Safari, Siamak Mohammadi:
LORAP: Low-Overhead Power and Reliability-Aware Task Mapping Based on Instruction Footprint for Real-Time Applications. DSD 2017: 364-367 - 2015
- Junwhan Ahn, Sungjoo Yoo, Onur Mutlu, Kiyoung Choi:
PIM-enabled instructions: a low-overhead, locality-aware processing-in-memory architecture. ISCA 2015: 336-348 - 2013
- Kristian F. D. Rietveld, Harry A. G. Wijshoff:
Quantifying Energy Usage in Data Centers through Instruction-count Overhead. SMARTGREENS 2013: 189-198 - 2012
- Jaroslav Sykora, Roman Bartosinski, Lukas Kohout, Martin Danek, Petr Honzík:
Reducing Instruction Issue Overheads in Application-Specific Vector Processors. DSD 2012: 600-607 - Muneeb Khan, Andreas Sembrant, Erik Hagersten:
Low Overhead Instruction-Cache Modeling Using Instruction Reuse Profiles. SBAC-PAD 2012: 260-269 - 2011
- Ji Gu, Hui Guo:
Reducing Power and Energy Overhead in Instruction Prefetching for Embedded Processor Systems. Int. J. Handheld Comput. Res. 2(4): 42-58 (2011) - 2010
- Demid Borodin, Ben H. H. Juurlink:
Protective redundancy overhead reduction using instruction vulnerability factor. Conf. Computing Frontiers 2010: 319-326 - 2009
- Asadollah Shahbahrami, Ben H. H. Juurlink:
Performance Improvement of Multimedia Kernels by Alleviating Overhead Instructions on SIMD Devices. APPT 2009: 389-407 - 2006
- Vikki Tang, Joran Siu, Alexander Vasilevskiy, Marcel Mitran:
A framework for reducing instruction scheduling overhead in dynamic compilers. CASCON 2006: 54-66 - 2005
- Hongkyu Kim, D. Scott Wills, Linda M. Wills:
Reducing Operand Communication Overhead using Instruction Clustering for Multimedia Application. ISM 2005: 345-352 - 2002
- Francisco Rodríguez, José Carlos Campelo, Juan José Serrano:
A Memory Overhead valuation of the Interleaved Signature Instruction Stream. DFT 2002: 225-232 - 2000
- Murali Annavaram, Gary S. Tyson, Edward S. Davidson:
Instruction overhead and data locality effects in superscalar processors. ISPASS 2000: 95-100 - 1984
- Robert G. Wedig, Marc A. Rose:
The Reduction of Branch Instruction Execution Overhead Using Structured Control Flow. ISCA 1984: 119-125
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