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Publication search results
found 7 matches
- 2023
- Kibeom Hong, Seogkyu Jeon, Junsoo Lee, Namhyuk Ahn, Kunhee Kim, Pilhyeon Lee, Daesik Kim, Youngjung Uh, Hyeran Byun:
AesPA-Net: Aesthetic Pattern-Aware Style Transfer Networks. ICCV 2023: 22701-22710 - Kibeom Hong, Seogkyu Jeon, Junsoo Lee, Namhyuk Ahn, Kunhee Kim, Pilhyeon Lee, Daesik Kim, Youngjung Uh, Hyeran Byun:
AesPA-Net: Aesthetic Pattern-Aware Style Transfer Networks. CoRR abs/2307.09724 (2023) - 2014
- Youngjung Ahn, Yongsuk Lee, Jin-Young Choi, Gyungho Lee, Dongkyun Ahn:
Monitoring Translation Lookahead Buffers to Detect Code Injection Attacks. Computer 47(7): 66-72 (2014) - 2009
- Hyun-Woo Lee, Won-Joo Yun, Young-Kyoung Choi, Hyang-Hwa Choi, Jong-Jin Lee, Ki-Han Kim, Shin-Deok Kang, Ji-Yeon Yang, Jae-Suck Kang, Hyeng-Ouk Lee, Dong-Uk Lee, Sujeong Sim, Young-Ju Kim, Won-Jun Choi, Keun-Soo Song, Sang-Hoon Shin, Hyung-Wook Moon, Seung-Wook Kwack, Jung-Woo Lee, Nak-Kyu Park, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Byong-Tae Chung:
A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS. ISSCC 2009: 140-141 - 2008
- Won-Joo Yun, Hyun-Woo Lee, Dongsuk Shin, Shin-Deok Kang, Ji-Yeon Yang, Hyeng-Ouk Lee, Dong-Uk Lee, Sujeong Sim, Young-Ju Kim, Won-Jun Choi, Keun-Soo Song, Sang-Hoon Shin, Hyang-Hwa Choi, Hyung-Wook Moon, Seung-Wook Kwack, Jung-Woo Lee, Young-Kyoung Choi, Nak-Kyu Park, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Ye Seok Yang:
A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology. ISSCC 2008: 282-283 - 2007
- Ki-Won Lee, Joo-Hwan Cho, Byoung-Jin Choi, Geun-Il Lee, Ho-Don Jung, Woo-Young Lee, Ki-Chon Park, Yongsuk Joo, Jaehoon Cha, Young-Jung Choi, Patrick B. Moran, Jin-Hong Ahn:
A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL. IEEE J. Solid State Circuits 42(11): 2369-2377 (2007) - 2006
- Dong-Uk Lee, Hyun-Woo Lee, Ki Chang Kwean, Young-Kyoung Choi, Hyong Uk Moon, Seung-Wook Kwack, Shin-Deok Kang, Kwan-Weon Kim, Yong Ju Kim, Young-Jung Choi, Patrick B. Moran, Jin-Hong Ahn, Joong Sik Kih:
A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL. ISSCC 2006: 547-556
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